 |
FPGA CentralWorld's 1st FPGA Portal |
|
|
|
|||||||
| Verilog comp.lang.verilog newsgroup / usenet |
|
|
|
 |
|
|
LinkBack | Thread Tools | Display Modes |
12-02-2005, 12:20 AM
|
|||
|
|||
Timing analysis for latch-based design in Design Compiler.
In Design Compiler, a balanced relative slack is prefered for
latch-based design. Can anybody tell me why?I don't quite understand why it can reduce delay costs and optimize near-critical path. Usually we just need to reduce the critical path, why near-critical path is needed here? Thanks, 
|
|
12-02-2005, 05:06 AM
|
|||
|
|||
|
Re: Timing analysis for latch-based design in Design Compiler.
Latch-based design is not timing friendly. In some cases it can solve
critical path. For example, some posedge FlipFlops' outputs go through combinational logic and the destination side is a negedge FF. The path is half clock cycle, if you replace the negedge FF by a low enable latch, you can borrow time from the next stage of the pipeline. But you have to make sure next stage is not time critical. Nandy www.nandigits.com Netlist debug/ECO in GUI mode.
|
|
| Bookmarks |
«
Help : Code works in synthesizer (silos), but warnings w/ webpack
|
Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
»
| Thread Tools | |
| Display Modes | |
Linear Mode
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Verilog based PCB design flow? | Petter Gustad | Verilog | 5 | 04-14-2010 07:24 PM |
| warning when using design compiler | sravan reddy | Verilog | 1 | 08-17-2005 09:05 AM |
| ANNOUNCE: X-Tek Releases X-Amin HDL Design/Analysis Suite | X-Tek Corporation | Verilog | 0 | 06-01-2005 01:12 AM |
| Physical Compiler Vs Design Complier | whizkid | Verilog | 1 | 11-03-2004 06:55 PM |
| parameters for Routability estimation and analysis during RTL stages of the design. | santhosh | Verilog | 1 | 08-21-2003 06:52 PM |
All times are GMT +1. The time now is 04:15 AM.
