FPGA Central

Hi anyone,

i'm reading intro. to verilog and am confusing on these two things.
Aren't they the same? task, module, and function seem to do the same
thing. Which one should one stick to if the target is to have
synthesizable verilog design. Thank you for your help.

The following rules distinguish tasks from functions:

# A function shall execute in one simulation time unit;
a task can contain time-controlling statements.

# A function cannot enable a task;
a task can enable other tasks or functions.

# A function shall have at least one input type argument
and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.

# A function shall return a single value;
a task shall not return a value.


difference between a module and task/function can be equated as
differnce between class and it's functions in C++.

"Linh Hoang" <[email protected]> wrote in message news:[email protected]..
> Hi anyone,
>
> i'm reading intro. to verilog and am confusing on these two things.
> Aren't they the same? task, module, and function seem to do the same
> thing. Which one should one stick to if the target is to have
> synthesizable verilog design. Thank you for your help.
>

Hi Linh,

A module is a bit different beast than a task or function.

A module defines a 'concurrently' executing model, essentially
directly modeling hardware.
E.g. : Ports on the top-level module become pins on the chip after synthesis.

Tasks and functions execute 'sequentially'. That is, they get called
as specific times (not concurrently) and execute their statements
one-by-one (after each other).

All three are synthesizable.

Rob