FPGA Central

Hi ,
I am trying to write a synchronizer in verilog, which will synchronize
between 2 clocks,
a signal, lets call it, "set_done" is assreted and driven by a state
machine that works with the high frequency clock and other state
machine that works with the low frquency clock should read it and de-
asseret it.
as much as I know that the state machines can't write-read to/from the
same register.
do you have any ideas how can I implement it ?
thanks in advance
-Amir

On Nov 28, 6:50 am, Amir <sting...@gmail.com> wrote:
> Hi ,
> I am trying to write a synchronizer in verilog, which will synchronize
> between 2 clocks,
> a signal, lets call it, "set_done" is assreted and driven by a state
> machine that works with the high frequency clock and other state
> machine that works with the low frquency clock should read it and de-
> asseret it.
> as much as I know that the state machines can't write-read to/from the
> same register.
> do you have any ideas how can I implement it ?
> thanks in advance
> -Amir

A technique I've used extensively uses a request and ack approach.
The "set_done" signal you want is an XOR from two flops in the
different clock domains. To assert the set_done, the flop in the set
domain is set to the invert of the flop in the ack domain. To ack
from the other time domain, the flop in that domain is set to the
value of the flop in the first domain. Both domains can look at the
XOR and get the "set_done" polarity. You only need to make sure your
system is designed to avoid issuing a set before the previous set has
been acked.

- John_H

Amir wrote:

> I am trying to write a synchronizer in verilog, which will synchronize
> between 2 clocks,
> a signal, lets call it, "set_done" is assreted and driven by a state
> machine that works with the high frequency clock and other state
> machine that works with the low frquency clock should read it and de-
> asseret it.
> as much as I know that the state machines can't write-read to/from the
> same register.
> do you have any ideas how can I implement it ?

I would use a synchronized handshake:

fast _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
data ___-----valid--------_________
ready ___------------------_________

slow __----____----____----____----____----
ack __________----------------____________
ackQ __________________----------------____
data __________________--valid---------

-- Mike Treseler