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  #1 (permalink)  
Old 11-18-2006, 07:47 AM
Davy
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Default Static Method in SystemVerilog?

Hi all,

As we all know, static variable is used to hold just one copy of the
variable in all instances from the same class.

But what's static method mainly used for (I have found many of them
when reading Mentor's AVM code)? I have read SystemVerilog Spec. It
seems static method is used to access static variable? Is my
understanding right? Thanks!

Code:
//-- Static method prototype---
static function int do_sth()
endfunction


Best regards,
Davy

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  #2 (permalink)  
Old 11-18-2006, 10:15 AM
AdamRose
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Posts: n/a
Default Re: Static Method in SystemVerilog?


Davy wrote:

> Hi all,
>
> As we all know, static variable is used to hold just one copy of the
> variable in all instances from the same class.
>
> But what's static method mainly used for (I have found many of them
> when reading Mentor's AVM code)? I have read SystemVerilog Spec. It
> seems static method is used to access static variable? Is my
> understanding right? Thanks!
>


Suppose you have a class A with a "normal" variable x :

class A;
int x;
endclass

There is one copy of x in each instance of A, and each instance is
different.

So if I go :

A a1 , a2;

a1 = new;
a2 = new;

a1.x =3;
a2.x = 4;

Then there are two copies of x, with values 3 and 4 respectively.

Static variables on the other hand are shared between all instances of
the class ( in fact, you can refer to them without an instance of the
class even existing ) and there is precisely one copy of the variable
in question.

So if I go

class A;
static int y;
endclass

A::y = 4;

This variable takes the value 4 no matter how many instances of A I
have created.

Inside the class, however, I can refer directly to "y" rather than
A::y, since A is a member of the class A.

Adam.

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  #3 (permalink)  
Old 11-18-2006, 06:20 PM
AdamRose
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Posts: n/a
Default Re: Static Method in SystemVerilog?


BTW you might be interested in the new avm discussion group that has
recently been set up. It's on
http://groups-beta.google.com/group/avm-users


On Nov 18, 9:15 am, "AdamRose" <Adam_R...@mentor.com> wrote:
> Davy wrote:
> > Hi all,

>
> > As we all know, static variable is used to hold just one copy of the
> > variable in all instances from the same class.

>
> > But what's static method mainly used for (I have found many of them
> > when reading Mentor's AVM code)? I have read SystemVerilog Spec. It
> > seems static method is used to access static variable? Is my
> > understanding right? Thanks!Suppose you have a class A with a "normal" variable x :

>
> class A;
> int x;
> endclass
>
> There is one copy of x in each instance of A, and each instance is
> different.
>
> So if I go :
>
> A a1 , a2;
>
> a1 = new;
> a2 = new;
>
> a1.x =3;
> a2.x = 4;
>
> Then there are two copies of x, with values 3 and 4 respectively.
>
> Static variables on the other hand are shared between all instances of
> the class ( in fact, you can refer to them without an instance of the
> class even existing ) and there is precisely one copy of the variable
> in question.
>
> So if I go
>
> class A;
> static int y;
> endclass
>
> A::y = 4;
>
> This variable takes the value 4 no matter how many instances of A I
> have created.
>
> Inside the class, however, I can refer directly to "y" rather than
> A::y, since A is a member of the class A.
>
> Adam.


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  #4 (permalink)  
Old 11-20-2006, 02:35 AM
Davy
Guest
 
Posts: n/a
Default Re: Static Method in SystemVerilog?

Hi Adam,

Now I understand static variable more preciously
And can you tell me why use static method (i.e. static function) in
class?

Best regards,
Davy

AdamRose wrote:
> Davy wrote:
>
> > Hi all,
> >
> > As we all know, static variable is used to hold just one copy of the
> > variable in all instances from the same class.
> >
> > But what's static method mainly used for (I have found many of them
> > when reading Mentor's AVM code)? I have read SystemVerilog Spec. It
> > seems static method is used to access static variable? Is my
> > understanding right? Thanks!
> >

>
> Suppose you have a class A with a "normal" variable x :
>
> class A;
> int x;
> endclass
>
> There is one copy of x in each instance of A, and each instance is
> different.
>
> So if I go :
>
> A a1 , a2;
>
> a1 = new;
> a2 = new;
>
> a1.x =3;
> a2.x = 4;
>
> Then there are two copies of x, with values 3 and 4 respectively.
>
> Static variables on the other hand are shared between all instances of
> the class ( in fact, you can refer to them without an instance of the
> class even existing ) and there is precisely one copy of the variable
> in question.
>
> So if I go
>
> class A;
> static int y;
> endclass
>
> A::y = 4;
>
> This variable takes the value 4 no matter how many instances of A I
> have created.
>
> Inside the class, however, I can refer directly to "y" rather than
> A::y, since A is a member of the class A.
>
> Adam.


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  #5 (permalink)  
Old 11-20-2006, 07:46 AM
Davy
Guest
 
Posts: n/a
Default Re: Static Method in SystemVerilog?

Hi,

I have find a article about SV's static method. But can all static
method be replaced with automatic method?

http://www.project-veripage.com/sv_class_4.php

Best regards,
Davy

Davy wrote:
> Hi Adam,
>
> Now I understand static variable more preciously
> And can you tell me why use static method (i.e. static function) in
> class?
>
> Best regards,
> Davy
>
> AdamRose wrote:
> > Davy wrote:
> >
> > > Hi all,
> > >
> > > As we all know, static variable is used to hold just one copy of the
> > > variable in all instances from the same class.
> > >
> > > But what's static method mainly used for (I have found many of them
> > > when reading Mentor's AVM code)? I have read SystemVerilog Spec. It
> > > seems static method is used to access static variable? Is my
> > > understanding right? Thanks!
> > >

> >
> > Suppose you have a class A with a "normal" variable x :
> >
> > class A;
> > int x;
> > endclass
> >
> > There is one copy of x in each instance of A, and each instance is
> > different.
> >
> > So if I go :
> >
> > A a1 , a2;
> >
> > a1 = new;
> > a2 = new;
> >
> > a1.x =3;
> > a2.x = 4;
> >
> > Then there are two copies of x, with values 3 and 4 respectively.
> >
> > Static variables on the other hand are shared between all instances of
> > the class ( in fact, you can refer to them without an instance of the
> > class even existing ) and there is precisely one copy of the variable
> > in question.
> >
> > So if I go
> >
> > class A;
> > static int y;
> > endclass
> >
> > A::y = 4;
> >
> > This variable takes the value 4 no matter how many instances of A I
> > have created.
> >
> > Inside the class, however, I can refer directly to "y" rather than
> > A::y, since A is a member of the class A.
> >
> > Adam.


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  #6 (permalink)  
Old 11-20-2006, 09:48 AM
AdamRose
Guest
 
Posts: n/a
Default Re: Static Method in SystemVerilog?


Davy,

Typically it's for some kind of housekeeping information.

For example :

class A;
static local int a_count = 0;
function new();
a_count++;
endfunction

static function int get_a_count();
return a_count;
endfunction
endclass

Now you can use get_a_count t to see how many instances of A ever got
created. If you want to do this outside of A, you can just go
A::get_a_count().

In the example above, a_count is both static and local, and we only
have read access to a_count via get_a_count. This is quite correct,
since nothing other than the constructor of A should have write access
to a_count.

Adam.

Davy wrote:

> Hi Adam,
>
> Now I understand static variable more preciously
> And can you tell me why use static method (i.e. static function) in
> class?
>
> Best regards,
> Davy
>
> AdamRose wrote:
> > Davy wrote:
> >
> > > Hi all,
> > >
> > > As we all know, static variable is used to hold just one copy of the
> > > variable in all instances from the same class.
> > >
> > > But what's static method mainly used for (I have found many of them
> > > when reading Mentor's AVM code)? I have read SystemVerilog Spec. It
> > > seems static method is used to access static variable? Is my
> > > understanding right? Thanks!
> > >

> >
> > Suppose you have a class A with a "normal" variable x :
> >
> > class A;
> > int x;
> > endclass
> >
> > There is one copy of x in each instance of A, and each instance is
> > different.
> >
> > So if I go :
> >
> > A a1 , a2;
> >
> > a1 = new;
> > a2 = new;
> >
> > a1.x =3;
> > a2.x = 4;
> >
> > Then there are two copies of x, with values 3 and 4 respectively.
> >
> > Static variables on the other hand are shared between all instances of
> > the class ( in fact, you can refer to them without an instance of the
> > class even existing ) and there is precisely one copy of the variable
> > in question.
> >
> > So if I go
> >
> > class A;
> > static int y;
> > endclass
> >
> > A::y = 4;
> >
> > This variable takes the value 4 no matter how many instances of A I
> > have created.
> >
> > Inside the class, however, I can refer directly to "y" rather than
> > A::y, since A is a member of the class A.
> >
> > Adam.


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  #7 (permalink)  
Old 11-20-2006, 10:03 AM
Davy
Guest
 
Posts: n/a
Default Re: Static Method in SystemVerilog?

Hi Adam,

Thanks a lot!
I understand. Static function is used to do job that share with all the
instance of one class (or as you said: housekeeping). So, they may
always do with static variable.

Best regards,
Davy

AdamRose wrote:
> Davy,
>
> Typically it's for some kind of housekeeping information.
>
> For example :
>
> class A;
> static local int a_count = 0;
> function new();
> a_count++;
> endfunction
>
> static function int get_a_count();
> return a_count;
> endfunction
> endclass
>
> Now you can use get_a_count t to see how many instances of A ever got
> created. If you want to do this outside of A, you can just go
> A::get_a_count().
>
> In the example above, a_count is both static and local, and we only
> have read access to a_count via get_a_count. This is quite correct,
> since nothing other than the constructor of A should have write access
> to a_count.
>
> Adam.
>
> Davy wrote:
>
> > Hi Adam,
> >
> > Now I understand static variable more preciously
> > And can you tell me why use static method (i.e. static function) in
> > class?
> >
> > Best regards,
> > Davy
> >
> > AdamRose wrote:
> > > Davy wrote:
> > >
> > > > Hi all,
> > > >
> > > > As we all know, static variable is used to hold just one copy of the
> > > > variable in all instances from the same class.
> > > >
> > > > But what's static method mainly used for (I have found many of them
> > > > when reading Mentor's AVM code)? I have read SystemVerilog Spec. It
> > > > seems static method is used to access static variable? Is my
> > > > understanding right? Thanks!
> > > >
> > >
> > > Suppose you have a class A with a "normal" variable x :
> > >
> > > class A;
> > > int x;
> > > endclass
> > >
> > > There is one copy of x in each instance of A, and each instance is
> > > different.
> > >
> > > So if I go :
> > >
> > > A a1 , a2;
> > >
> > > a1 = new;
> > > a2 = new;
> > >
> > > a1.x =3;
> > > a2.x = 4;
> > >
> > > Then there are two copies of x, with values 3 and 4 respectively.
> > >
> > > Static variables on the other hand are shared between all instances of
> > > the class ( in fact, you can refer to them without an instance of the
> > > class even existing ) and there is precisely one copy of the variable
> > > in question.
> > >
> > > So if I go
> > >
> > > class A;
> > > static int y;
> > > endclass
> > >
> > > A::y = 4;
> > >
> > > This variable takes the value 4 no matter how many instances of A I
> > > have created.
> > >
> > > Inside the class, however, I can refer directly to "y" rather than
> > > A::y, since A is a member of the class A.
> > >
> > > Adam.


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