FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-25-2005, 06:08 PM
vikramts
Guest
 
Posts: n/a
Default Simulation Data extraction

Hello

I would like to make plots of variables used in my codes and I realise
that Verilog-AMS only provides transient analysis. I figured it would make
sense to try and sample some points and store values in a text file or
something,which I could use in Matlab or Excel.

Can someone tell me how I should do this?Are tere any tools in SimVision
for Verilog-AMS for this purpose?I have tried using $fopen,$fdisplay but I
am not able to understand the proper method of usage.

Any help/source references would be greatly appreciated!Beginner in
Verilog-AMS and SimVision here!!!!

-Vikram

Reply With Quote
  #2 (permalink)  
Old 01-25-2005, 11:48 PM
Jason Zheng
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

vikramts wrote:
> Hello
>
> I would like to make plots of variables used in my codes and I realise
> that Verilog-AMS only provides transient analysis. I figured it would make
> sense to try and sample some points and store values in a text file or
> something,which I could use in Matlab or Excel.
>
> Can someone tell me how I should do this?Are tere any tools in SimVision
> for Verilog-AMS for this purpose?I have tried using $fopen,$fdisplay but I
> am not able to understand the proper method of usage.
>
> Any help/source references would be greatly appreciated!Beginner in
> Verilog-AMS and SimVision here!!!!
>
> -Vikram
>

You can simply use $monitoor or $display tasks to print to stdout, just
make sure every line that you print out has some unique identifier, such
as this:

checkpoint1: a = ... b = ...
checkpoint2: ...
....


then you can use a simple grep command to extract all those lines
(assuming your simulator's log file is verilog.log):

grep checkpoint verilog.log > checkpoints.txt

Ta-da!
Reply With Quote
  #3 (permalink)  
Old 01-26-2005, 03:21 AM
vikramts
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

Hi Jason

Does simulation data get written to verilog.log even if you are using a
code in Verilog-AMS and compiling it through SimVision(instead of
NCVerilog)?



Reply With Quote
  #4 (permalink)  
Old 01-26-2005, 08:17 PM
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

Hi Jason

Does simulation data get written to verilog.log even if you are using a
code in Verilog-AMS and compiling it through SimVision(instead of
NCVerilog)?



Reply With Quote
  #5 (permalink)  
Old 01-26-2005, 09:34 PM
[email protected]
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

Hi.

You could try this:

integer rslts;

// open results file, write header
rslts=$fopen("tb_results.txt"); // Name of text file.
$fdisplay(rslts, "testbench results"); // Text File Header.
$fdisplay(rslts);
$fwrite(rslts, "\n"); // Insert blank line.

// Format data.
$fdisplay(rslts, "\t%s\t%s", "address", "data"); // Setup header.
$fdisplay(rslts, "\t%h\t%h", addr_for, data_out); // Write Data.

Hope this helps,

Jeremy

vikramts wrote:
> Hello
>
> I would like to make plots of variables used in my codes and I

realise
> that Verilog-AMS only provides transient analysis. I figured it would

make
> sense to try and sample some points and store values in a text file

or
> something,which I could use in Matlab or Excel.
>
> Can someone tell me how I should do this?Are tere any tools in

SimVision
> for Verilog-AMS for this purpose?I have tried using $fopen,$fdisplay

but I
> am not able to understand the proper method of usage.
>
> Any help/source references would be greatly appreciated!Beginner in
> Verilog-AMS and SimVision here!!!!
>
> -Vikram


Reply With Quote
  #6 (permalink)  
Old 01-26-2005, 11:02 PM
Jason Zheng
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

vikramts wrote:
> Hi Jason
>
> Does simulation data get written to verilog.log even if you are using a
> code in Verilog-AMS and compiling it through SimVision(instead of
> NCVerilog)?
>
>
>

Regardless of the simulator/compiler choice, you specify the name of the
log file through some simulator option. Some have a default log file,
and the names are likely to differ. Your best bet is to find out what
simulator option is to specify the log file and then use that option to
run the simulator.

-jz
Reply With Quote
  #7 (permalink)  
Old 02-02-2005, 02:21 AM
vikramts
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

Hi Jeremy

Ok,this might sound elementary...but I did try the code you gave,and I am
able to write into my file.Now how can I get data points from the
simulations that I run using SimVision(for Verilog-AMS)?

In other words,how do I sample the waveform at certain points and get a
table of values of all quantities(eg:voltage,current) versus time(so that
i can make plots of voltage1 vs current or voltage2 vs voltage1 etc etc)?



Reply With Quote
  #8 (permalink)  
Old 02-02-2005, 02:35 AM
[email protected]
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

Perhaps something like

forever
#delay $fdisplay(rslts, "%t %h %h", $time, voltage, current);
Where delay is the desired time between data points.

Reply With Quote
  #9 (permalink)  
Old 02-04-2005, 04:29 AM
vikramts
Guest
 
Posts: n/a
Default Re: Simulation Data extraction

Hey!

It worked!Thanks so much!That was really helpful!
Does the Cadence-AMS Simulator have an option to make plots of chosen
variables?Or is it advisable to use the extracted data in another graphing
tool?

Vikram

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Export data from Modelsim DW Verilog 5 02-11-2005 05:36 PM
Bangalore, India -- VLSI/ASIC/CAD Tech Lead, Parasitic Extraction Jerry Bires Verilog 1 05-29-2004 01:48 AM
PLI: manipulating reg data through VPI Girish Venkataramani Verilog 4 11-17-2003 11:09 PM
data recorder examples? bob Verilog 0 10-31-2003 08:52 PM
Data Structure Viewer Jim Wu Verilog 2 08-18-2003 11:51 AM


All times are GMT +1. The time now is 02:29 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved