FPGA Central

Hi,

I have a parallel driver in verilog generate by a wizard tool in
Quartus II.
So i must reverse the 16 first bits in the parallel port (because the
16 first bits correspond to a data bus and it is inverted)

Here is the code: http://pastebin.com/f196e46c9

I tried a lot of changes, but without result.
I am bad in verilog and VHDL barely better, so I ask your help.

thanks.

(ps: sorry for my english but I'm french.)

Charly wrote:
> Hi,
>
> I have a parallel driver in verilog generate by a wizard tool in
> Quartus II.
> So i must reverse the 16 first bits in the parallel port (because the
> 16 first bits correspond to a data bus and it is inverted)
>
> Here is the code: http://pastebin.com/f196e46c9
>
> I tried a lot of changes, but without result.
> I am bad in verilog and VHDL barely better, so I ask your help.
>
> thanks.


Maybe a verilog function would do the trick.
Here's how I do it in vhdl:

function reverse (arg : unsigned)
return unsigned is
variable rev_v : unsigned(arg'reverse_range);
begin
for i in arg'range loop
rev_v(i) := arg(i);
end loop;
return rev_v;
end function;

-- Mike Treseler

(ps: sorry for my french and english but I'm north american)

On Jun 17, 1:36*pm, Mike Treseler <mtrese...@gmail.com> wrote:
> Charly wrote:
> > Hi,
>
> > I have a parallel driver in verilog generate by a wizard tool in
> > Quartus II.
> > So i must reverse the 16 first bits in the parallel port (because the
> > 16 first bits correspond to a data bus and it is inverted)
>
> > Here is the code:http://pastebin.com/f196e46c9
>
> > I tried a lot of changes, but without result.
> > I am bad in verilog and VHDL barely better, so I ask your help.
>
> > thanks.
>
> Maybe a verilog function would do the trick.
> Here's how I do it in vhdl:
>
> * *function reverse (arg : unsigned)
> * * * return unsigned is
> * * * variable rev_v : unsigned(arg'reverse_range);
> * *begin
> * * * for i in arg'range loop
> * * * * *rev_v(i) := arg(i);
> * * * end loop;
> * * * return rev_v;
> * *end function;
>
> * * * -- Mike Treseler
>
> (ps: sorry for my french and english but I'm north american)

Charly,

Here is how you can reverse bits in verilog. You can make a function/
task out of this:

module reverse();
parameter WIDTH = 4;

reg [WIDTH-1:0] rev, data;
integer i;

initial
begin
data=4'b1110;

for (i=WIDTH-1; i >= 0; i=i-1)
rev[WIDTH-1-i]=data[i];

$display("data %b\t tmp %b",data,rev);

#5 $finish;
end
endmodule


Also I find that http://www.pastebin.cz/ has good syntax
highlighter for Verilog/VHDL for pasting so you may
want to use that in the future.