FPGA Central

Hi,

I have always used the following methodology for testing my verilog
modules:

1. Prepare a test bench that instantiates within itself the Design
under test (DUT);
2. Provide the stimuli (clock, reset, other inputs) to the DUT within
the testbench;
3. End the simulation with a $finish statement when all the required
amount of stimulus/ testing has been accomplished.

The test bench is compiled and simulated in one go. However, if I need
to test my DUT using live signals (not on the actual hardware, but
using the test bench environment), how can I do so? Do any of the
verilog simulators provide such a feature?

Thanks,
Kanchan

kb33 wrote:
[...]
>
> The test bench is compiled and simulated in one go. However, if I need
> to test my DUT using live signals (not on the actual hardware, but
> using the test bench environment), how can I do so? Do any of the
> verilog simulators provide such a feature?

Your first question should be, how do you get those live signals into
the Computer where you run the simulator on.

Once that is clear, there are basically two options, save the data to a
file and use the file I/O in your testbench to read them. The other is
to use a Co-Simulation approach via the Verilog PLI.

The Co-Simulation approach can be that you write your own Verilog PLI
code that accesses the data or you use one of the existing approaches
like MyHDL or Trusster.

With MyHDL http://myhdl.jandecaluwe.com/doku.php you can write the code
that accesses your data and feeds it to the DUT in Python.

With Trusster http://www.trusster.com/ you can do the same in C++.

Actually to be accurate, both systems, MyHDL and Trusster are much more
than just doing Co-Simulation, but in both that is a core functionality
that you can use to feed data into your DUT.

Cheers,

Guenter

Hi Guenter,

Thanks for mentioning Trusster. We also have a SystemVerilog version
up there as well now.

Both http://myhdl.jandecaluwe.com/doku.php and http://www.trusster.com
have well,documented, open-source, independent verification
frameworks.

Take Care,
Mike