FPGA Central

Hi,

I want to read and write into a buffer from another module without
first reading/writing it onto a port. Find my code snipet below-

module ABC ( clock ,
reset ,
InData ,
OutData ,
);

// Port Declarations

reg buff1[0:15][0:15];
reg buff2[0:15][0:15];

I want to write into buff1 from output of a verilog module, reorder
bits into buff2 and then pass it on to another module.

I could combine the three modules together which i want to avoid for
clarity.
I also could write it to a port and then read from it- which will
waste unnecessary resources and clock cycles.

Any suggestions ?

Kauser.

On Jun 18, 12:13*pm, Kausi <kauser.jo...@gmail.com> wrote:
> I want to read and write into a buffer from another module without
> first reading/writing it onto a port. Find my code snipet below-
>
> module *ABC ( clock * * * * ,
> * * * * * * * * * * * reset * * * * *,
> * * * * * * * * * * * InData * * * *,
> * * * * * * * * * * * OutData * * ,
> * * * * * * * * * * );
>
> * * * // Port Declarations
>
> * * * * * reg * * * *buff1[0:15][0:15];
> * * * * * reg * * * *buff2[0:15][0:15];
>
> I want to write into buff1 from output of a verilog module, reorder
> bits into buff2 and then pass it on to another module.

I'm not sure how this relates to the ports on your module ABC.

> I could combine the three modules together which i want to avoid for
> clarity.
> I also could write it to a port and then read from it- which will
> waste unnecessary resources and clock cycles.

What makes you think that passing data through a port
will "waste resources and clock cycles"? Ports are just
connections....
--
Jonathan Bromley

On Jun 18, 7:47*am, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
> On Jun 18, 12:13*pm, Kausi <kauser.jo...@gmail.com> wrote:
>
>
>
> > I want to read and write into a buffer from another module without
> > first reading/writing it onto a port. Find my code snipet below-
>
> > module *ABC ( clock * * * * ,
> > * * * * * * * * * * * reset * * * * *,
> > * * * * * * * * * * * InData * * * *,
> > * * * * * * * * * * * OutData * * ,
> > * * * * * * * * * * );
>
> > * * * // Port Declarations
>
> > * * * * * reg * * * *buff1[0:15][0:15];
> > * * * * * reg * * * *buff2[0:15][0:15];
>
> > I want to write into buff1 from output of a verilog module, reorder
> > bits into buff2 and then pass it on to another module.
>
> I'm not sure how this relates to the ports on your module ABC.
>
> > I could combine the three modules together which i want to avoid for
> > clarity.
> > I also could write it to a port and then read from it- which will
> > waste unnecessary resources and clock cycles.
>
> What makes you think that passing data through a port
> will "waste resources and clock cycles"? *Ports are just
> connections....
> --
> Jonathan Bromley

I think the point is that his memory arrays cannot be
directly used as module ports. For simulation you could
use direct hierarchy access to the memory, but for
synthesis the only reasonable approach is to put all
access to the memory array in the module where it is
defined. Address and data bus ports to the memory
can certainly be routed via module ports without any
additional "resources and clock cycles" but the
memories themselves cannot be directly accessed for
synthesis from another module, since the RAM elements
inferred would not allow this.

Regards,
Gabor

On Thu, 18 Jun 2009 07:14:58 -0700 (PDT), gabor wrote:

>I think the point is that his memory arrays cannot be
>directly used as module ports.

True; Verilog ports must be simple vectors.

>For simulation you could
>use direct hierarchy access to the memory, but for
>synthesis the only reasonable approach is to put all
>access to the memory array in the module where it is
>defined. Address and data bus ports to the memory
>can certainly be routed via module ports without any
>additional "resources and clock cycles" but the
>memories themselves cannot be directly accessed for
>synthesis from another module, since the RAM elements
>inferred would not allow this.

I agree with all of this, but I still don't get it.

If you have a memory block, then it can only be
accessed through its address and data signals,
whether or not it's in the same module. Passing
those address and data signals through ports of
the enclosing module costs nothing.

If a given module can access any and all locations
of a memory simultaneously, then that isn't a
memory (except in the Verilog LRM-jargon sense);
it's just a large collection of flip-flops. You
can easily gain access to that from another module,
simply by flattening the memory's contents to a
single big vector and passing said vector through
the module port. That's tiresome, but not difficult.

In summary, I agree with Gabor but I still don't
understand what the OP was asking.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
j[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Sorry about the way my question was posted. But i did get the answer
from the discussion.

Thanks.