FPGA Central

Hello everybody,

I just start to learn systemverilog for my verification job and want
to get some tips from expeirenced people here:

1. Tools:
Are there any free/trial version of systemverilog tools (simulator)
that I can play with my toy program?
2. Verilog
It is necessary to learn verilog before systemverilog?
3. Book
I am reading the books "Verification Methodology Manual for
SystemVerilog" and "Systemverilog for verification". I feel VMM too
difficult for me. SystemVerilog for Verification is very good for
beginner, Any tip for other good books are wekcome as well as how to
read it.
4. framework
VMM is a big software framework. How to learn it quickly? For example,
how to print "hello world, your RTL is 100% correct!"

Hongqing Hu

> 2. Verilog
> It is necessary to learn verilog before systemverilog?
No, but it will make it alot easier. One of my junior QA engineers signed
up for a SystemVerilog class, but didn't know verilog. She did complete the
coarse but had alot of difficulty. On occasions, I would teach her how to
do the lab work in verilog so she would have a basic idea of why the system
verilog was better. Or even how to do the system verilog.
While it can be done, I suggest getting a good beginning verilog book it
will help alot.

On Dec 20, 7:47 am, humann <hongqing...@gmail.com> wrote:
> Hello everybody,
>
> I just start to learn systemverilog for my verification job and want
> to get some tips from expeirenced people here:
>
> 1. Tools:
> Are there any free/trial version of systemverilog tools (simulator)
> that I can play with my toy program?
> 2. Verilog
> It is necessary to learn verilog before systemverilog?
> 3. Book
> I am reading the books "Verification Methodology Manual for
> SystemVerilog" and "Systemverilog for verification". I feel VMM too
> difficult for me. SystemVerilog for Verification is very good for
> beginner, Any tip for other good books are wekcome as well as how to
> read it.
> 4. framework
> VMM is a big software framework. How to learn it quickly? For example,
> how to print "hello world, your RTL is 100% correct!"
>
> Hongqing Hu

Hongqing,

I also think learning Verilog first is a good idea.

Instead of VMM, perhaps look at Teal/Truss (http://www.trusster.com/).
You may also be interested in the book "Hardware Verification With
SystemVerilog: An Object-oriented Framework".

Good luck,
/Ed

Hi Hongqing

On Dec 20 2007, 5:47 pm, humann <hongqing...@gmail.com> wrote:
> Hello everybody,
>
> I just start to learn systemverilog for my verification job and want
> to get some tips from expeirenced people here:
>
> 1. Tools:
> Are there any free/trial version of systemverilog tools (simulator)
> that I can play with my toy program?

SV-Design stuff is available with ModelsimXE - other than that every
thing is commercial software AFAIK.

> 2. Verilog
> It is necessary to learn verilog before systemverilog?

Yes, I would say it is a pre-requisite.

> 3. Book
> I am reading the books "Verification Methodology Manual for
> SystemVerilog" and "Systemverilog for verification". I feel VMM too
> difficult for me.

Check out www.systemverilog.us and specifically our book on
"Pragmatic Approach to VMM adoption" - we focused precisely on this
angle!

> SystemVerilog for Verification is very good for
> beginner, Any tip for other good books are wekcome as well as how to
> read it.

Did you look at SVA? Again I have co-authored a SVA book, besides
that there are atleast 2 more books on this topic.

> 4. framework
> VMM is a big software framework. How to learn it quickly? For example,
> how to print "hello world, your RTL is 100% correct!"

program hello_world;
`include "vmm.sv"
vmm_log log;
initial begin : test
log = new ("Example", "0");
`vmm_note (log, "hello world, your RTL is 100% correct!");
$finish;
end : test
endprogram : hello_world

Run it like:

vcs -sverilog -ntb_opts rvm hello.sv
simv +vmm_log_default=note

HTH
Ajeetha, CVC
www.noveldv.com

On Jan 4, 5:51 pm, "cvc.train...@gmail.com" <cvc.train...@gmail.com>
wrote:
> Hi Hongqing
>
> On Dec 20 2007, 5:47 pm, humann <hongqing...@gmail.com> wrote:
>
> > Hello everybody,
>
> > I just start to learn systemverilog for my verification job and want
> > to get some tips from expeirenced people here:
>
> > 1. Tools:
> > Are there any free/trial version of systemverilog tools (simulator)
> > that I can play with my toy program?
>
> SV-Design stuff is available with ModelsimXE - other than that every
> thing is commercial software AFAIK.
>
> > 2. Verilog
> > It is necessary to learn verilog before systemverilog?
>
> Yes, I would say it is a pre-requisite.
After learning SystemVerilog for two months, I found the Language "E"
is a quasi
pre-requisite for SystemVerilog, too. I learn SystemVerilog for my
Verification Job.
What I want to do with SV are:
- derive test plan from specification and code it in Coverage point
- develop test cases and check functional closure.

But books in this area use "E" as its example code.
(for exmaple: Functional Verification Coverage Measurement and
Analysis; Standardized Functional Verification)

> > 3. Book
> > I am reading the books "Verification Methodology Manual for
> > SystemVerilog" and "Systemverilog for verification". I feel VMM too
> > difficult for me.
>
> Check outwww.systemverilog.usand specifically our book on
> "Pragmatic Approach to VMM adoption" - we focused precisely on this
> angle!
Yes. I have bought and read this book. It is GREAT. After reading it,
I can modify the other's code in a week.
It is a MUST-HAVE book for anyone who wants to learn how to use VMM
after understanding the basic SystemVerilog Syntax.

But I can't find any lab code in your book, which is obviously deleted
from release.

> > SystemVerilog for Verification is very good for
> > beginner, Any tip for other good books are wekcome as well as how to
> > read it.
>
> Did you look at SVA? Again I have co-authored a SVA book, besides
> that there are atleast 2 more books on this topic.
Yes, please recommend them. If it is really as good as "Pragmatic
Approach to VMM adoption", I won't hesitate to buy it.

> > 4. framework
> > VMM is a big software framework. How to learn it quickly? For example,
> > how to print "hello world, your RTL is 100% correct!"
>
> program hello_world;
> `include "vmm.sv"
> vmm_log log;
> initial begin : test
> log = new ("Example", "0");
> `vmm_note (log, "hello world, your RTL is 100% correct!");
> $finish;
> end : test
> endprogram : hello_world
>
> Run it like:
>
> vcs -sverilog -ntb_opts rvm hello.sv
> simv +vmm_log_default=note
>
> HTH
> Ajeetha, CVCwww.noveldv.com

You will find that PSL(Accelera) has alot of similarities to System Verilog
as well. Since PSL and openVera were sort of merged to form SystemVerilog.

There were alot of languages from the EDA community fighting for dominance
in the verification arena. System Verilog seems to have won out.

I believe Synop
"humann" <[email protected]> wrote in message
news:[email protected]..
> On Jan 4, 5:51 pm, "cvc.train...@gmail.com" <cvc.train...@gmail.com>
> wrote:
>> Hi Hongqing
>>
>> On Dec 20 2007, 5:47 pm, humann <hongqing...@gmail.com> wrote:
>>
>> > Hello everybody,
>>
>> > I just start to learn systemverilog for my verification job and want
>> > to get some tips from expeirenced people here:
>>
>> > 1. Tools:
>> > Are there any free/trial version of systemverilog tools (simulator)
>> > that I can play with my toy program?
>>
>> SV-Design stuff is available with ModelsimXE - other than that every
>> thing is commercial software AFAIK.
>>
>> > 2. Verilog
>> > It is necessary to learn verilog before systemverilog?
>>
>> Yes, I would say it is a pre-requisite.
> After learning SystemVerilog for two months, I found the Language "E"
> is a quasi
> pre-requisite for SystemVerilog, too. I learn SystemVerilog for my
> Verification Job.
> What I want to do with SV are:
> - derive test plan from specification and code it in Coverage point
> - develop test cases and check functional closure.
>
> But books in this area use "E" as its example code.
> (for exmaple: Functional Verification Coverage Measurement and
> Analysis; Standardized Functional Verification)
>
>> > 3. Book
>> > I am reading the books "Verification Methodology Manual for
>> > SystemVerilog" and "Systemverilog for verification". I feel VMM too
>> > difficult for me.
>>
>> Check outwww.systemverilog.usand specifically our book on
>> "Pragmatic Approach to VMM adoption" - we focused precisely on this
>> angle!
> Yes. I have bought and read this book. It is GREAT. After reading it,
> I can modify the other's code in a week.
> It is a MUST-HAVE book for anyone who wants to learn how to use VMM
> after understanding the basic SystemVerilog Syntax.
>
> But I can't find any lab code in your book, which is obviously deleted
> from release.
>
>> > SystemVerilog for Verification is very good for
>> > beginner, Any tip for other good books are wekcome as well as how to
>> > read it.
>>
>> Did you look at SVA? Again I have co-authored a SVA book, besides
>> that there are atleast 2 more books on this topic.
> Yes, please recommend them. If it is really as good as "Pragmatic
> Approach to VMM adoption", I won't hesitate to buy it.
>
>> > 4. framework
>> > VMM is a big software framework. How to learn it quickly? For example,
>> > how to print "hello world, your RTL is 100% correct!"
>>
>> program hello_world;
>> `include "vmm.sv"
>> vmm_log log;
>> initial begin : test
>> log = new ("Example", "0");
>> `vmm_note (log, "hello world, your RTL is 100% correct!");
>> $finish;
>> end : test
>> endprogram : hello_world
>>
>> Run it like:
>>
>> vcs -sverilog -ntb_opts rvm hello.sv
>> simv +vmm_log_default=note
>>
>> HTH
>> Ajeetha, CVCwww.noveldv.com

"humann" <[email protected]> wrote in message
news:[email protected]..
> On Jan 4, 5:51 pm, "cvc.train...@gmail.com" <cvc.train...@gmail.com>
> wrote:
>> > 1. Tools:
>> > Are there any free/trial version of systemverilog tools (simulator)
>> > that I can play with my toy program?
>>
>> SV-Design stuff is available with ModelsimXE - other than that every
>> thing is commercial software AFAIK.

Actually, (Xilinx) Modelsim/XE no longer supports Systemverilog --
that was removed as of 6.2g (June 2007.) 6.2c was the last free
simulator to support Systemverilog (for design.) And Mentor's
Modelsim Student Edition 6.3p1 (May 2007) was the last (free)
student version to support Systemverilog. The later versions removed
it.

Modelsim Altera Edition 6.1g might still support it, but the level of
support in 6.1g is barely usable. (A lot of improvement occured between
the core Modelsim engine 6.1 and 6.2b.)

> After learning SystemVerilog for two months, I found the Language "E"
> is a quasi

Why do you fell 'E' is pre-requisite? I'm in the opposite situation.
I already know Systemverilog (Design) fairly well. I'm a beginner in
Systemverilog testbench/verification, but our customer will use 'E'
instead, which I've never touched before.