FPGA Central

Hi

I need help with the following verilog code. When I try to synthesize
it,
I get a lot of "Signal xxxxxx is never used or assigned."
The verilog code is translated from the following c code:

volatile char BUTTON;
// more input declaration here
volatile char WAIT_ONE; // WAIT_ONE always evalutes to 1
// more output declaration here
volatile char LED;
volatile unsigned int GLOBALCOUNTER; // end IO declaration

int main(){
int blink_times=0;
int i,j;
while(WAIT_ONE){
for (i=0;i<1000000;i++) if (BUTTON != 0) {blink_times++;break;}
for (j=0;j<blink_times;j++) {
for (i=0;i<100000;i++) LED=1;
for (i=0;i<100000;i++) LED=0;
}
}
}

Translated verilog code:

module logic(clk,reset,main_BUTTON,main_LED);
input clk;
input reset;
reg [31:0] main_PC;
input signed [7:0] main_BUTTON;
reg signed [7:0] WAIT_ONE;
output signed [7:0] main_LED;
reg signed [7:0] main_LED;
reg [31:0] GLOBALCOUNTER;
reg signed [31:0] main_blink_times;
reg signed [31:0] main_i;
reg signed [31:0] main_j;
reg signed [31:0] main_r000000007;
reg signed [31:0] main_r000000008;
reg signed [31:0] main_r000000006;
reg signed [31:0] main_r000000022;
reg signed [31:0] main_r000000023;
reg signed [31:0] main_r000000021;
reg signed [31:0] main_r000000024;
reg signed [31:0] main_r000000020;
reg signed [31:0] main_r000000029;
reg signed [31:0] main_r000000039;
reg signed [31:0] main_r000000095;
reg signed [31:0] main_r000000094;
reg signed [31:0] main_r000000099;
reg signed [31:0] main_r000000098;
reg signed [31:0] main_r000000058;
reg signed [31:0] main_r000000106;
reg signed [31:0] main_r000000105;
reg signed [31:0] main_r000000072;
reg signed [31:0] main_r000000113;
reg signed [31:0] main_r000000112;
reg signed [31:0] main_r000000078;
reg signed [31:0] main_r000000118;
reg signed [31:0] main_r000000082;
reg signed [31:0] main_r000000083;
reg signed [31:0] main_r000000081;
reg signed [31:0] main_r000000087;

always @(posedge clk) GLOBALCOUNTER=GLOBALCOUNTER+1;
always @(posedge reset)
begin
main_PC=0;
WAIT_ONE=8'b11111111;
GLOBALCOUNTER=0;
end

always @(posedge clk)
begin
case (main_PC)
0 : begin main_PC=main_PC+1; end
1 : begin
main_blink_times = 0; // 2 ldc
main_r000000007 = WAIT_ONE; // 7 cvt
main_r000000008 = 0; // 8 ldc
main_r000000006 = (main_r000000007 !==
main_r000000008)?1:0 ;
main_PC=(main_r000000006)?(main_PC+1)16);
end
2 : begin
main_i = 0; // 35 ldc
main_PC=main_PC+1;
end
3 : begin
main_r000000022 = main_BUTTON; // 22 cvt
main_r000000023 = 0; // 23 ldc
main_r000000021 = (main_r000000022 !==
main_r000000023)?1:0 ;
main_r000000024 = 0; // 24 ldc
main_r000000020 = (main_r000000021 ===
main_r000000024)?1:0 ;
main_PC=(main_r000000020)?(5)main_PC+1);
end
4 : begin
main_r000000029 = 1; // 29 ldc
main_blink_times = main_blink_times +
main_r000000029; // 28
main_PC=6;
end
5 : begin
main_r000000039 = 1; // 39 ldc
main_i = main_i + main_r000000039; // 92
main_r000000095 = 1000000; // 95 ldc
main_r000000094 = (main_r000000095 <= main_i)?1:0 ;
// 94
main_PC=(main_r000000094)?(main_PC+1)3);
end
6 : begin
main_r000000099 = 0; // 99 ldc
main_r000000098 = (main_r000000099 <
main_blink_times)?1:0 ;
main_PC=(main_r000000098)?(main_PC+1)14);
end
7 : begin
main_j = 0; // 75 ldc
main_PC=main_PC+1;
end
8 : begin
main_i = 0; // 54 ldc
main_PC=main_PC+1;
end
9 : begin
main_LED = 1; // 52 ldc
main_r000000058 = 1; // 58 ldc
main_i = main_i + main_r000000058; // 103
main_r000000106 = 100000; // 106 ldc
main_r000000105 = (main_r000000106 <= main_i)?1:0 ;
// 105
main_PC=(main_r000000105)?(main_PC+1)9);
end
10 : begin
main_i = 0; // 68 ldc
main_PC=main_PC+1;
end
11 : begin
main_LED = 0; // 66 ldc
main_r000000072 = 1; // 72 ldc
main_i = main_i + main_r000000072; // 110
main_r000000113 = 100000; // 113 ldc
main_r000000112 = (main_r000000113 <= main_i)?1:0 ;
// 112
main_PC=(main_r000000112)?(main_PC+1)11);
end
12 : begin
main_r000000078 = 1; // 78 ldc
main_j = main_j + main_r000000078; // 116
main_r000000118 = (main_blink_times <= main_j)?1:0 ;
// 118
main_PC=(main_r000000118)?(main_PC+1)8);
end
13 : begin
main_PC=15;
end
14 : begin
main_j = 0; // 122 ldc
main_PC=main_PC+1;
end
15 : begin
main_r000000082 = WAIT_ONE; // 82 cvt
main_r000000083 = 0; // 83 ldc
main_r000000081 = (main_r000000082 !==
main_r000000083)?1:0 ;
main_PC=(main_r000000081)?(2)main_PC+1);
end
16 : begin
main_r000000087 = 0; // 87 ldc
main_PC=99999999;
end
99999999 : begin main_PC=99999999; end
endcase
end
endmodule

The warning messages:
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <main_BUTTON> is never used.
WARNING:Xst:1306 - Output <main_LED> is never assigned.
WARNING:Xst:1780 - Signal <main_r000000006> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000007> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000008> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000020> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000021> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000022> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000023> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000024> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000029> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000039> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000105> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000106> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000112> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000058> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000113> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000072> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000118> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000081> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000082> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000078> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000083> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000087> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000094> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000095> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000098> is never used or assigned.
WARNING:Xst:1780 - Signal <main_r000000099> is never used or assigned.
WARNING:Xst:646 - Signal <WAIT_ONE> is assigned but never used.
WARNING:Xst:1780 - Signal <main_i> is never used or assigned.
WARNING:Xst:1780 - Signal <main_j> is never used or assigned.
WARNING:Xst:1780 - Signal <main_blink_times> is never used or assigned.

I'm sure this is not a problem with constraint file, because constraint
file hasn't being applied yet. These are messages from synthesis stage,
and translation stage hasn't occurred yet. I simply can't see what's
wrong with translated verilog code. I've considered it might be
over-optimization, but looking at the code, it doesn't seem to allow
that to happen. If I can't find answers to this problem, my c2verilog
translation project is doomed

please help.

> always @(posedge clk) GLOBALCOUNTER=GLOBALCOUNTER+1;
> always @(posedge reset)
> begin
> main_PC=0;
> WAIT_ONE=8'b11111111;
> GLOBALCOUNTER=0;
> end
>
> always @(posedge clk)

Ok, I've got it figure out. Xst gives really bad error messages, while
synplify
gives readable messages. The above code should be changed to:

always @(posedge clk) GLOBALCOUNTER=GLOBALCOUNTER+1;
always @(posedge clk or posedge reset)
if (reset===1) begin
main_PC=0;
WAIT_ONE=8'b11111111;
GLOBALCOUNTER=0;
end else
begin
......
......

It synthesizes and works! Harayyyy!