FPGA Central

World's 1st FPGA Portal

		FPGA Groups > NewsGroup > Verilog
*NCSIM .fsdb dump vs .shm dump*

Verilog comp.lang.verilog newsgroup / usenet

LinkBack

Thread Tools

Display Modes

#1 (permalink)

11-06-2005, 05:27 PM

eda_employee

Guest

Posts: n/a

NCSIM *.fsdb dump vs *.shm dump

For a large mixed-language (VHDL-93, Verilog-2001) SoC design,
I've noticed that dumping the entire testbench hieararchy (from top)
seems to take a very long time (surprise surprise...)

But there is a large performance difference between dumping a
Debussy-compatible database (*.fsdb) and Signalscan/Simvision (*.shm)
If I use NCSIM's built-in $shm_open/$shm_probe, the simulation runs
much faster. Is this what everyone else is seeing?

(I'm guessing that shm-output uses NCSIM's internal-routines, and
aren't bottlenecked by the PLI/VPI external-interface.)

Bookmarks

« Re: Gracias por todo, me ha servido de ayuda QID1 | Any Verilog-A simulator for free download? »

Thread Tools
Show Printable Version Email this Page
Display Modes
Linear Mode Switch to Hybrid Mode Switch to Threaded Mode

Posting Rules
You may not post new threads You may not post replies You may not post attachments You may not edit your posts BB code is On Smilies are On [IMG] code is On HTML code is Off Trackbacks are On Pingbacks are On Refbacks are On Forum Rules

Similar Threads
Thread	Thread Starter	Forum	Replies	Last Post
[NCsim] How to force re-computation ?	Olivier FAURAX	Verilog	2	10-06-2005 06:10 PM
how to use fsdb dump	Karthikeyan Subramaniyam	Verilog	1	10-01-2005 09:46 AM
[OT] bit-flip with NCSim	Olivier FAURAX	Verilog	2	09-12-2005 10:35 PM
Value Change Dump Viewer	Uwe Bonnes	Verilog	9	07-16-2005 12:53 AM
Viewing Dump File(.vcd file)	pgh	Verilog	2	10-27-2004 08:59 AM

All times are GMT +1. The time now is 07:54 AM.