FPGA Central

Is there a compact way of creating multiple instances of a circuit?

Instead of repeating something like the following 32 times, can I do
this in some kind of a loop with indexing.

Channel U_Channel0 ( .clk(clk),
.reset(reset),
.delay_time(delay_time),
.gate_width(gate_width),
.threshold(threshold),
.ch(5'd0),
.din(db[0]),
.dout(dout[0]),
.empty(empty),
.half_full(half_full),
.full(full) );

Channel U_Channel1 ( .clk(clk),
.reset(reset),
.delay_time(delay_time),
.gate_width(gate_width),
.threshold(threshold),
.ch(5'd1),
.din(db[1]),
.dout(dout[1]),
.empty(empty),
.half_full(half_full),
.full(full) );

thanks

Bill

You want to use generate. See below. (NOTE: I did not do a syntax check)


generate
genvar i;
for (i=0; i<=32; i = i +1)
begin : u
Channel U_Channel0 ( .clk(clk),
.reset(reset),
.delay_time(delay_time),
.gate_width(gate_width),
.threshold(threshold),
.ch(i),
.din(db[i]),
.dout(dout[i]),
.empty(empty),
.half_full(half_full),
.full(full) );
end
endgenerate


"Bill Burris" <[email protected]> wrote in message
news:fmm5n1$dra$[email protected]..
> Is there a compact way of creating multiple instances of a circuit?
>
> Instead of repeating something like the following 32 times, can I do this
> in some kind of a loop with indexing.
>
> Channel U_Channel0 ( .clk(clk),
> .reset(reset),
> .delay_time(delay_time),
> .gate_width(gate_width),
> .threshold(threshold),
> .ch(5'd0),
> .din(db[0]),
> .dout(dout[0]),
> .empty(empty),
> .half_full(half_full),
> .full(full) );
>
> Channel U_Channel1 ( .clk(clk),
> .reset(reset),
> .delay_time(delay_time),
> .gate_width(gate_width),
> .threshold(threshold),
> .ch(5'd1),
> .din(db[1]),
> .dout(dout[1]),
> .empty(empty),
> .half_full(half_full),
> .full(full) );
>
> thanks
>
> Bill

On Jan 16, 7:00*pm, Bill Burris <wbur...@ualberta.ca> wrote:
> Is there a compact way of creating multiple instances of a circuit?
>
> Instead of repeating something like the following 32 times, can I do
> this in some kind of a loop with indexing.

In addition to the generate loop suggested by Dwayne, you can also
declare instance arrays if your connection scheme is simple and
regular enough. The only problem for your case would be the
incrementing channel number, which pretty much requires a generate
loop if you want to make the number of instances parameterizable.

On Jan 16, 8:05 pm, sh...@cadence.com wrote:
> On Jan 16, 7:00 pm, Bill Burris <wbur...@ualberta.ca> wrote:
>
> > Is there a compact way of creating multiple instances of a circuit?
>
> > Instead of repeating something like the following 32 times, can I do
> > this in some kind of a loop with indexing.
>
> In addition to the generate loop suggested by Dwayne, you can also
> declare instance arrays if your connection scheme is simple and
> regular enough. The only problem for your case would be the
> incrementing channel number, which pretty much requires a generate
> loop if you want to make the number of instances parameterizable.

I like the array of instances for things like this - even when dealing
with
parameterized numbers. It CAN be more concise than a generate,
depending on
how your data is organized.

Bill, the trick is handling the signals that are unique for
each instance. For each of these you need to create a single "wide"
version
of the net, with all the signals concatenated. I'll assume your din,
dout
signals are 8 bits:

// Inputs
wire [ 2 * 5 - 1 : 0 ] ch_wide = { 5'd1, 5'd0 };
wire [ 2 * 8 - 1 : 0 ] din_wide = { db[1], db[0] };

// Outputs
wire [ 2 * 8 - 1 : 0 ] dout_wide;
assign { dout[ 1 ], dout[ 0 ] } = dout_wide;

The above becomes cleaner and easier in SystemVerilog with packed
arrays:

// Inputs
wire [ 1 : 0 ] [ 4 : 0 ] ch_wide = { 5'd1, 5'd0 };
wire [ 1 : 0 ] [ 7 : 0 ] din_wide = { db[1], db[0] };

// Outputs
wire [ 1 : 0 ] [ 7 : 0 ] dout_wide;
assign { dout[ 1 ], dout[ 0 ] } = dout_wide;

If the instance number ( i.e 2 above) is another parameter, it get's
trickier -
you'd probably need to do the assignments procedurally, but it still
works.
Again you'll find SystemVerilog packed arrays a big help here.

Then, the instanciation looks like:

Channel U_Channel[ 1 : 0 ]
(
.clk(clk),
.reset(reset),
.delay_time(delay_time),
.gate_width(gate_width),
.threshold(threshold),
.ch( ch_wide ),
.din( din_wide ),
.dout( dout_wide ),
.empty(empty),
.half_full(half_full),
.full(full)
);

It all depends on where the data is coming from / used. I tend to
use the array of instances more, so the data passing back and forth
is already in a "wide" form (or packed array in SystemVerilog) and the
extra assignments are not needed.

Generates are good to, but sometimes indexing into a wide bus within
the
loop can get ugly.

--Mark

Thanks for the help everyone. The books I have don't cover generate and
instance arrays.

Bill

On Jan 17, 10:55 pm, "gtw...@pacbell.net" <gtw...@pacbell.net> wrote:
> On Jan 16, 8:05 pm, sh...@cadence.com wrote:
>
> > On Jan 16, 7:00 pm, Bill Burris <wbur...@ualberta.ca> wrote:
>
> > > Is there a compact way of creating multiple instances of a circuit?
>
> > > Instead of repeating something like the following 32 times, can I do
> > > this in some kind of a loop with indexing.
>
> > In addition to the generate loop suggested by Dwayne, you can also
> > declare instance arrays if your connection scheme is simple and
> > regular enough. The only problem for your case would be the
> > incrementing channel number, which pretty much requires a generate
> > loop if you want to make the number of instances parameterizable.
>
> I like the array of instances for things like this - even when dealing
> with
> parameterized numbers. It CAN be more concise than a generate,
> depending on
> how your data is organized.
>
> Bill, the trick is handling the signals that are unique for
> each instance. For each of these you need to create a single "wide"
> version
> of the net, with all the signals concatenated. I'll assume your din,
> dout
> signals are 8 bits:
>
> // Inputs
> wire [ 2 * 5 - 1 : 0 ] ch_wide = { 5'd1, 5'd0 };
> wire [ 2 * 8 - 1 : 0 ] din_wide = { db[1], db[0] };
>
> // Outputs
> wire [ 2 * 8 - 1 : 0 ] dout_wide;
> assign { dout[ 1 ], dout[ 0 ] } = dout_wide;
>
> The above becomes cleaner and easier in SystemVerilog with packed
> arrays:
>
> // Inputs
> wire [ 1 : 0 ] [ 4 : 0 ] ch_wide = { 5'd1, 5'd0 };
> wire [ 1 : 0 ] [ 7 : 0 ] din_wide = { db[1], db[0] };
>
> // Outputs
> wire [ 1 : 0 ] [ 7 : 0 ] dout_wide;
> assign { dout[ 1 ], dout[ 0 ] } = dout_wide;
>
> If the instance number ( i.e 2 above) is another parameter, it get's
> trickier -
> you'd probably need to do the assignments procedurally, but it still
> works.
> Again you'll find SystemVerilog packed arrays a big help here.
>
> Then, the instanciation looks like:
>
> Channel U_Channel[ 1 : 0 ]
> (
> .clk(clk),
> .reset(reset),
> .delay_time(delay_time),
> .gate_width(gate_width),
> .threshold(threshold),
> .ch( ch_wide ),
> .din( din_wide ),
> .dout( dout_wide ),
> .empty(empty),
> .half_full(half_full),
> .full(full)
> );
>
> It all depends on where the data is coming from / used. I tend to
> use the array of instances more, so the data passing back and forth
> is already in a "wide" form (or packed array in SystemVerilog) and the
> extra assignments are not needed.
>
> Generates are good to, but sometimes indexing into a wide bus within
> the
> loop can get ugly.
>
> --Mark

HI Mike,

what this statement will do in the code above u have mentioned.
Channel U_Channel[ 1 : 0 ]

You probably have books written bassed on the verilog 93.

The generate and instance arrays were added later.

"Bill Burris" <[email protected]> wrote in message
news:fmo5j1$d5j$[email protected]..
> Thanks for the help everyone. The books I have don't cover generate and
> instance arrays.
>
> Bill

The code mike created will do exactly what the orignal poster code will do.
It creates two instances of "Channel". The major difference are the names
before the names were U_Channel0, no the name would be U_Channel[0]. Also
previously the use had to code the correct bits to the instatiated module.
Now the connects are grabbed automatically from an array. The developer
would have to code the arrays manually still.

I like the generate method, but that is personal. I started with VHDL and
for...generate statements, therfore the generate in verilog feels more
comfortable to me.

<[email protected]> wrote in message
news:[email protected]..
> On Jan 17, 10:55 pm, "gtw...@pacbell.net" <gtw...@pacbell.net> wrote:
>> On Jan 16, 8:05 pm, sh...@cadence.com wrote:
>>
>> > On Jan 16, 7:00 pm, Bill Burris <wbur...@ualberta.ca> wrote:
>>
>> > > Is there a compact way of creating multiple instances of a circuit?
>>
>> > > Instead of repeating something like the following 32 times, can I do
>> > > this in some kind of a loop with indexing.
>>
>> > In addition to the generate loop suggested by Dwayne, you can also
>> > declare instance arrays if your connection scheme is simple and
>> > regular enough. The only problem for your case would be the
>> > incrementing channel number, which pretty much requires a generate
>> > loop if you want to make the number of instances parameterizable.
>>
>> I like the array of instances for things like this - even when dealing
>> with
>> parameterized numbers. It CAN be more concise than a generate,
>> depending on
>> how your data is organized.
>>
>> Bill, the trick is handling the signals that are unique for
>> each instance. For each of these you need to create a single "wide"
>> version
>> of the net, with all the signals concatenated. I'll assume your din,
>> dout
>> signals are 8 bits:
>>
>> // Inputs
>> wire [ 2 * 5 - 1 : 0 ] ch_wide = { 5'd1, 5'd0 };
>> wire [ 2 * 8 - 1 : 0 ] din_wide = { db[1], db[0] };
>>
>> // Outputs
>> wire [ 2 * 8 - 1 : 0 ] dout_wide;
>> assign { dout[ 1 ], dout[ 0 ] } = dout_wide;
>>
>> The above becomes cleaner and easier in SystemVerilog with packed
>> arrays:
>>
>> // Inputs
>> wire [ 1 : 0 ] [ 4 : 0 ] ch_wide = { 5'd1, 5'd0 };
>> wire [ 1 : 0 ] [ 7 : 0 ] din_wide = { db[1], db[0] };
>>
>> // Outputs
>> wire [ 1 : 0 ] [ 7 : 0 ] dout_wide;
>> assign { dout[ 1 ], dout[ 0 ] } = dout_wide;
>>
>> If the instance number ( i.e 2 above) is another parameter, it get's
>> trickier -
>> you'd probably need to do the assignments procedurally, but it still
>> works.
>> Again you'll find SystemVerilog packed arrays a big help here.
>>
>> Then, the instanciation looks like:
>>
>> Channel U_Channel[ 1 : 0 ]
>> (
>> .clk(clk),
>> .reset(reset),
>> .delay_time(delay_time),
>> .gate_width(gate_width),
>> .threshold(threshold),
>> .ch( ch_wide ),
>> .din( din_wide ),
>> .dout( dout_wide ),
>> .empty(empty),
>> .half_full(half_full),
>> .full(full)
>> );
>>
>> It all depends on where the data is coming from / used. I tend to
>> use the array of instances more, so the data passing back and forth
>> is already in a "wide" form (or packed array in SystemVerilog) and the
>> extra assignments are not needed.
>>
>> Generates are good to, but sometimes indexing into a wide bus within
>> the
>> loop can get ugly.
>>
>> --Mark
>
> HI Mike,
>
> what this statement will do in the code above u have mentioned.
> Channel U_Channel[ 1 : 0 ]
>