FPGA Central

Hi, all
Under multi-master enviroment, if there are two masters which

are accessing the same slave at the same time. One master wants to


write one byte to the slave, the other master wants to write two bytes


to the slave. The first master sends the message " Start + Slave


address + Ack + byte one + Stop ", while the second master sends the


message " Start + Slave address + Ack + byte one + Ack + byte two+ Ack


+ Stop".
When the first master wants to send stop, while the second master wants



to send first bit of the second byte, who will win the arbitration?


And if the second master sends the message "start+Start + Slave address

+ Ack + byte one + Ack + byte two+ Ack + restart+slave address+..."
,how can I guarantee the bus generate a restart signal?


My question is related descriptions on I2C spec ver2.1 P13. " In other
word, arbitration isn't allowed between
*A repeated start condition and a data bit
*A stop condition and a data bit
*A repeated start condition and a stop condition. "
So question comes. If such cases happen, how to do with arbitration ?


thanks.