FPGA Central

Hi

I have Verilog top mixed design. I want to dump "VHDL variables" in
the fsdb file (debussy).
Can any one suggest me, how to do this?
Note: $fsdbdumpvars is for pure verilog desings, right?

Thanks
--
Karthikeyan Subramaniyam,
Design Verification Engineer,
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.

Karthik,
Look at Debussy's documentation for xact details. Here is what
I found via a quick google search:

http://support.aldec.com/KnowledgeBa...spx?aid=000344

FSDB_DUMP: process
begin
fsdbDumpfile("simdata.fsdb");
fsdbDumpvars(0, "");
wait;
end process;

> Note: $fsdbdumpvars is for pure verilog desings, right?

AFAIK, any "$" call is PLI, hence works in Verilog, some tools might
extend it to mixed designs - for instance $vcdpluson in VCS-MX works
for both VHDL & Verilog.

A good reference (via google) is:
http://www2.cic.org.tw/training/trai...ebussy0407.pdf

I got the following:

Approach 1 : fsdbDumpVariable FLI
Dump to FSDB file directly
Need to specify the variables separately
The naming rules of variables are different between
different simulators (ModelSim and NC-VHDL)
Ex: fsdbDumpVariable /system/line__85/flag

HTH
Ajeetha
www.noveldv.com

Karthikeyan Subramaniyam wrote:
> Hi
>
> I have Verilog top mixed design. I want to dump "VHDL variables" in
> the fsdb file (debussy).
> Can any one suggest me, how to do this?
> Note: $fsdbdumpvars is for pure verilog desings, right?
>
> Thanks
> --
> Karthikeyan Subramaniyam,
> Design Verification Engineer,
> TooMuch Semiconductor Solutions Pvt. Ltd.
> www.toomuchsemi.com
> A Bangalore based startup specialising on services in EDA & Verification.