FPGA Central

Hi,
Does anyone know how I can convert my verilog code to VHDL?

Stanley

<[email protected]> wrote in message news:<yWYob.63946$[email protected]>. ..
> Hi,
> Does anyone know how I can convert my verilog code to VHDL?

Ummm, by hand?

-a

by hand
another way is using EDA tools likes Visual HDL and HDL Designer's Serise.
(and synthesis tools can export vhdl netlist from verilog RTL)


<[email protected]> wrote in message
news:yWYob.63946$[email protected]..
> Hi,
> Does anyone know how I can convert my verilog code to VHDL?
>
> Stanley
>
>

The main question is: do we want conversion on RTL or Gate levels?
For RTL, I completely agree that "by hand" approach is the safest one.
For gatelevel, just dump your design to vhdl format after running
synthesis, or load your verilog gatelevel to the synthesis tool and
then save it in vhdl format.

Regards,
Alexander

"Kim Hyun-Gyu" <[email protected]> wrote in message news:<bo73sp$khq$[email protected]>...
> by hand
> another way is using EDA tools likes Visual HDL and HDL Designer's Serise.
> (and synthesis tools can export vhdl netlist from verilog RTL)
>
>
> <[email protected]> wrote in message
> news:yWYob.63946$[email protected]..
> > Hi,
> > Does anyone know how I can convert my verilog code to VHDL?
> >
> > Stanley
> >
> >