FPGA Central

Hi,

I am working on an ASIC using Synopsys design compiler, Cadence Silicon
Ensemble, and Synopsys Primetime. Primetime is telling me that my
register file (8 bit wide 32 registers) is prohibiting me from reaching my
target clock frequency which is 250 MHz.

Can anyone suggest a way code the register file in Verilog such that this
critical path is removed?

Thanks,

-Rohit

I assume the critical path to be the 32:1 mux for reading from the
register file. Instead of 32:1 mux try using smaller muxes (like 4:1)
in a tree structure and place registers between each stage. This will
increase the read latency.

"Kiran" <[email protected]> wrote in message
news:[email protected] om...
> I assume the critical path to be the 32:1 mux for reading from the
> register file. Instead of 32:1 mux try using smaller muxes (like 4:1)
> in a tree structure and place registers between each stage. This will
> increase the read latency.

If muxes *are* being used, perhaps an enable for each register followed by a
wide OR would produce better ASIC-specific results since wide gates should
implement very well.

reg [4:0] Sel;
reg [7:0] RegFile [31:0];

reg [7:0] RegFileRd;
integer i;
always @( RegFile or Sel )
begin
RegFileRd = 32'h0000_0000;
for( i=0; i<32; i=i+1)
RegFileRd = RegFileRd | (Sel == i ? RegFile[i] : 32'h0000_0000);
// 32 5-input ANDs feed 32x8 2-input ANDs followed by 8 32-input ORs
end

"mr_camel" <[email protected]> wrote in message news:<[email protected] alkaboutprogramming.com>...
> Hi,
>
> I am working on an ASIC using Synopsys design compiler, Cadence Silicon
> Ensemble, and Synopsys Primetime. Primetime is telling me that my
> register file (8 bit wide 32 registers) is prohibiting me from reaching my
> target clock frequency which is 250 MHz.
>
> Can anyone suggest a way code the register file in Verilog such that this
> critical path is removed?
>
> Thanks,
>
> -Rohit

Even an FPGA can manage this but one would use 16b rams rather than
registers.

You don't say much about the periphery. If the address lines and mux
outputs are flopped, then just a 32->1 mux inside that pipe should be
easy. Sounds like you have siome extra logic paths either in the
address or output path or both.


regards

johnjakson_usa_com