 |
FPGA CentralWorld's 1st FPGA Portal |
|
|
09-02-2006, 09:38 PM
|
|||
|
|||
Re: generated clocks
"vic marks" <[email protected]> wrote in message news:63881$44f9bf51$50392791$[email protected] .. > Hi, > > I need a suggestion in handling the generated clocks for synthesis, and > DFT. > What kind of constraints would be used for generated-clocks during > synthesis, and DFT design. > Same constraints as with any other clock signal; namely, setup time and hold time for inputs, clock to output for outputs KJ 
|
|
09-03-2006, 10:34 AM
|
|||
|
|||
|
Re: generated clocks
If you are usinng DCyou can use the create_generated_clock constraint
Check out DC's man pages about usimg this command KJ wrote: > "vic marks" <[email protected]> wrote in message > news:63881$44f9bf51$50392791$[email protected] .. > > Hi, > > > > I need a suggestion in handling the generated clocks for synthesis, and > > DFT. > > What kind of constraints would be used for generated-clocks during > > synthesis, and DFT design. > > > Same constraints as with any other clock signal; namely, setup time and hold > time for inputs, clock to output for outputs > > KJ
|
 |
| Bookmarks |
| Thread Tools | |
| Display Modes | |
Linear Mode
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| please let me know what hardware is generated for this piece of verilog code | a | Verilog | 6 | 02-07-2006 08:10 AM |
| How to constain a internal generated clock in DC script? | Enchanter | Verilog | 1 | 01-11-2006 09:10 AM |
| Defining clocks in STA | reni | Verilog | 1 | 06-30-2005 10:25 AM |
| Is there any disadvantages in two clocks connect to a DFF through a MUX? | Ensoul Chee | Verilog | 1 | 10-26-2004 09:57 PM |
| Multiple clocks generation | Monib Khan | Verilog | 1 | 08-04-2003 06:10 PM |
All times are GMT +1. The time now is 03:02 AM.
