FPGA Central

Hi,

Can anybody tell me how to create a FIFO in verilog, in which I can read
and write in the same clock cycle. If the stack is initially empty and I
have read and write high, then data_out of should be equal to data_in.

Thanks,
Raji

Raji wrote:
> Hi,
>
> Can anybody tell me how to create a FIFO in verilog, in which I can read
> and write in the same clock cycle. If the stack is initially empty and I
> have read and write high, then data_out of should be equal to data_in.
>
> Thanks,
> Raji
>

Why would the read be high if the stack is empty? Wouldn't you check to
see if the stack is empty first before you request a read? It's possible
to do read and write at the same cycle but you need to have:

1. Space to write in
2. Data to read

This is the way I manage a FIFO that allows simultaneous read/write:

reg [1:0] write_ptr, read_ptr;
reg full;
wire empty, read_req, write_req;

assign empty = ~full & (write_ptr != read_ptr);

always @ (posedge clk)
if (reset) begin
write_ptr <= 2'b0;
read_ptr <= 2'b0;
full <= 1'b0;
end
else case ({read_req, write_req})
2'b01: begin
write_ptr <= write_ptr + 1;
read_ptr <= read_ptr;
full <= write_ptr == (read_ptr - 1);
end
2'b10: begin
write_ptr <= write_ptr;
read_ptr <= read_ptr + 1;
full <= 1'b0;
end
2'b11: begin
write_ptr <= write_ptr + 1;
read_ptr <= read_ptr + 1;
full <= full;
end
default: begin
write_ptr <= write_ptr;
read_ptr <= read_ptr;
full <= full;
end
endcase

Jason Zheng wrote:
> Raji wrote:
> > Hi,
> >
> > Can anybody tell me how to create a FIFO in verilog, in which I can
> > read and write in the same clock cycle. If the stack is initially
> > empty and I have read and write high, then data_out of should be
> > equal to data_in.
> >
> > Thanks,
> > Raji
> >
>
> Why would the read be high if the stack is empty? Wouldn't you check
> to see if the stack is empty first before you request a read? It's
> possible to do read and write at the same cycle but you need to have:
>
> 1. Space to write in
> 2. Data to read

It is possible to request a read from a FIFO without first checking to see
if it has any data. Simply perform the read, then later check whether the
FIFO actually gave you any data [in this case the "read" signal might be
better named "nstall" or "ready", and the "empty" signal becomes "nvalid"
attached to the output data].

If you want to be able to perform a simultaneous read and write from/to a
FIFO even when the FIFO is empty, then you will need to create a
combinatorial path round the FIFO that is active whenever the FIFO is empty.
As with most such things, the only limitation is the clock period.

John

--
John Penton - posting as an individual unless otherwise indicated.

"Raji" <[email protected]> wrote in message
news:[email protected] lkaboutprogramming.com...
> Hi,
>
> Can anybody tell me how to create a FIFO in verilog, in which I can read
> and write in the same clock cycle. If the stack is initially empty and I
> have read and write high, then data_out of should be equal to data_in.
>
> Thanks,
> Raji
>

I understand what your describing, but
1. You left out what kind of input/output you expect (in terms of flags, how
many of what type of buses...).
2. It doesn't seem possible because whatever block it's feeding would not
know data is ready unless the fifo told it that it contained data. You
could build a mux outside the fifo, and if the fifo is empty, take the
data
directly from the fifo's input. But only your level of a need for that
function
and results from synthesis could determine whether such a solution is
merited.
3. I have plenty of fifo models that work good, if the block your fifo is
feeding doesn't mind waiting 1 clock cycle.

BB