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Hi,

I'd like to ask a question about "Error loading design" error. My module
compiles fine without an error. However, when I tried to simulate it with
a testbench for the module, ModelSim gives an error message, saying "Error
loading design". I copied & pasted the error message and my code below. I
haven't been able to find out how to fix this error. If you see any
problem in my code, please let ne know.

Thanks.

vsim work.test_SaXSb
# vsim work.test_SaXSb
# Loading work.test_SaXSb
# Loading work.SaXSb
# ** Warning: (vsim-3009) [TSCALE] - Module 'SaXSb' does not have a
`timescale directive in effect, but previous modules do.
# Region: /test_SaXSb/X1
# ** Error: (vsim-3033) D:/ ....... /SaXSb.v(11): Instantiation of
'zero_check' failed. The design unit was not found.
# Region: /test_SaXSb/X1
# Searched libraries:
# work
# Loading work.exp_elem
# ** Warning: (vsim-3009) [TSCALE] - Module 'exp_elem' does not have a
`timescale directive in effect, but previous modules do.
# Region: /test_SaXSb/X1/E1
# Loading work.alpha_elem
# ** Warning: (vsim-3009) [TSCALE] - Module 'alpha_elem' does not have a
`timescale directive in effect, but previous modules do.
# Region: /test_SaXSb/X1/A1
# Error loading design


module SaXSb (Sx_val, Sx_exp, Sa, Sb);

input [7:0] Sa, Sb;
output [7:0] Sx_val, Sx_exp;

wire [7:0] Sx_val, Sx_exp;
wire [7:0] Sa_temp, Sb_temp;

parameter mask = 8'h0F;

zero_check(Sx_val, Sx_exp, Sa, Sb); // <= THIS IS LINE (11) WHERE THE
ERROR OCCURED

exp_elem E1 (.exp_val(Sa_temp), .index(Sa));
exp_elem E2 (.exp_val(Sb_temp), .index(Sb));

assign Sa_temp = wraparound_check(Sa_temp);

assign Sa_temp = Sa_temp & mask; // mask out 4 unnecessary MSB's
alpha_elem A1 (.alpha_val(Sb_temp), .index(Sa_temp));
assign Sx_val = Sb_temp;
assign Sx_exp = Sa_temp;

task zero_check;
inout [7:0] x_val, x_exp;
input [7:0] a, b;
reg [7:0] x_val, x_exp;

begin
if ((a==0)||(b==0)) begin
x_val = 8'h00;
x_exp = 8'h10; //if a==0 and b==0, Sx_val and
disable SaXSb; // Sx-exp values should not be
// modified by the codes below
end //if
end //begin

endtask

function wraparound_check;
input [7:0] a_temp;
begin
if (a_temp >= 15) wraparound_check = a_temp+1;
end
endfunction

endmodule

It looks like you are trying to call task zero_check outside of any
procedural code (i.e. not in an initial or always block). You can't
have procedural statements sitting naked at the module level.

An identifier followed by a parenthesized list at the module level
can only be an instantiation. Since you haven't provided an
instance name for it, it must be a UDP rather than a module.
But since you haven't provided a definition for such a UDP,
it tells you it can't find it.

[email protected] wrote:
> It looks like you are trying to call task zero_check outside of any
> procedural code (i.e. not in an initial or always block). You can't
> have procedural statements sitting naked at the module level.
>
> An identifier followed by a parenthesized list at the module level
> can only be an instantiation. Since you haven't provided an
> instance name for it, it must be a UDP rather than a module.
> But since you haven't provided a definition for such a UDP,
> it tells you it can't find it.
>
It appears to me that zero_check is a module, since it says
"instantiation failure." I'm guess he didn't put the file containing
zero_check in the modelsim project file.

-jz

Hi sharp,
Thanks much for your kind reply.

1)I'm not certain whether you meant that I must specify an instance name
when calling the task?
->As you can see at the bottom portion the code, zero_check is a task
inside the same module.

2)If I want to call a task, should I do so inside a procedural block?
->The reason why I called the task outside the procedural block is that
the parameters of the task are nets, which can't be LHS of an assignment
in procedural block.

3) Let's say I need to call tasks, functions and other modules from a
higher level module in a procedural construct and that the parameters(for
those tasks, functions and modules) and LHS of assignment in the
procedural block consists of both regs and nets.

Then do I need to declare temporary regs for the wires to use in
procedural block? And assign those temp regs back to wires outside the
procedural block?

Please let me know if my understanding is correct. If not, let me know
what I should do in such a case.

Hi sharp,
Thanks so much for your kind reply.
I'd like to ask a few question about your reply.

1) Can I call a module inside a procedural block? If so, is there any
conditions that I need to follow? (i.e., if the output parameters in the
module calling parameter list are nets, do I need to use temp nets to to
call the module inside a procedural block?)

2) Say I need to call tasks, functions and other modules from a higher
level module in a procedural construct and that the parameters(for those
tasks, functions and modules) and LHS of assignment in the procedural
block consists of both regs and nets.

Then do I need to declare temporary regs for the wires and assign those
temp regs back to wires outside the procedural block?

Please let me know if my understanding is correct. If not, let me know
what I should do in such a case. Thanks!

thomasc wrote:
> I'd like to ask a question about "Error loading design" error. My module
> compiles fine without an error. However, when I tried to simulate it with
> a testbench for the module, ModelSim gives an error message, saying "Error
> loading design". I copied & pasted the error message and my code below. I
> haven't been able to find out how to fix this error. If you see any
> problem in my code, please let ne know.

Hello,

as far as I know, you have to call the task from an always block,
initial block, or from another task.

HTH & HAND,
Stefan