FPGA Central

In Verilog or SystemVerilog, is it possible to do zero padding when
displaying an integer as in C/C++? Something equivalent to:

printf( "%05d", x );

Also is it possible to display in upper-case hex characters instead?

printf( "%X", h );

-- Amal

On Jun 22, 5:18*pm, Amal <akhailt...@gmail.com> wrote:
> In Verilog or SystemVerilog, is it possible to do zero padding when
> displaying an integer as in C/C++? *Something equivalent to:
>
> * printf( "%05d", x );

No, not by the 2005 IEEE standards. The 2009 draft standard currently
in balloting allows a width field in the format.

> Also is it possible to display in upper-case hex characters instead?
>
> * printf( "%X", h );

You get whatever case your implementation gives you. The standard
does not specify a case, and makes no distinction between %h and %H
(%x is nonstandard).