FPGA Central

World's 1st FPGA Portal

		FPGA Groups > NewsGroup > Verilog
Design Rule Cost in Synthesis

Verilog comp.lang.verilog newsgroup / usenet

#1 (permalink)

11-01-2004, 06:26 AM

whizkid

Guest

Posts: n/a

Design Rule Cost in Synthesis

what is the significance of Design Rule Cost in Synthesis ??

thanks
whizkid

Bookmarks

Thread Tools
Show Printable Version Email this Page
Display Modes
Linear Mode Switch to Hybrid Mode Switch to Threaded Mode

Posting Rules
You may not post new threads You may not post replies You may not post attachments You may not edit your posts BB code is On Smilies are On [IMG] code is On HTML code is Off Trackbacks are On Pingbacks are On Refbacks are On Forum Rules

Similar Threads
Thread	Thread Starter	Forum	Replies	Last Post
bottom up synthesis with parameterized design	Marco Lazar	Verilog	0	04-22-2004 07:38 PM
Low-cost ASIC tools	Brendan Lynskey	Verilog	2	09-27-2003 04:40 AM

All times are GMT +1. The time now is 02:33 AM.