FPGA Central

Down below is some code I wrote to implement "Data Memory" block from
my old textbook. The module has both mem_read and mem_write signals
going into it, which caused me to contemplate a bit :-)

I got the following questions with this approached that I chose:

1. I set the triggers to data_in and address. I suppose I could use
mem_read and mem_write as triggers. I actually did this but I was
picking the stale value when both mem_read and mem_write where 1. Do
you suggest going by the approach below? Any other comments ..?

2. I am setting 00 case to 32'bX. Do you suggest doing this? I
didn't know what else to put in there and I didn't want the data out
to be the "previous" value. But of course, I wasn't going to "read"
this 32'bX either. So the question is... would I rather have 32'bX
or previous data_out. What would you rather do in this case?

3. Is the below code going to blow during synthesis? (Question on
the side: Is there a simple free tool I can use to check if the code
is synthesizeable on my Win XP machine?)

module data_memory(
address,
data_in,
mem_read,
mem_write,
data_out);

parameter AW = 32; //address width
parameter RW = 32; //register width

input [AW-1:0] address;
input [RW-1:0] data_in;
output [RW-1:0] data_out;
input mem_read;
input mem_write;

reg [RW-1:0] register_array[AW-1:0];
reg [RW-1:0] data_out;

always @(data_in or address)
begin
case ({mem_write, mem_read}) //switch based on concatenation
2'b00: data_out <= 32'bX;
2'b01: data_out <= register_array[address];
2'b10: register_array[address] <= data_in;
2'b11:
begin
register_array[address] <= data_in;
data_out <= data_in;
end
endcase
end
endmodule


Thanks in advance,

Mahurshi Akilla

> Is there a simple free tool I can use to check if the code is
synthesizeable on my Win XP machine?

1. Install Icarus Verilog for Windows:
http://www.icarus.com/eda/verilog/

2. Run from the command prompt:
iverilog -tfpga -parch=virtex source_files(s)
Iverilog issues warning with line numbers on non-synthesizable
constructs.

-Alex

PS. register_array size has to be not AW-1 but 2^AW-1