FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-21-2007, 11:15 AM
designer
Guest
 
Posts: n/a
Default Cycle Accurate Modelling

Hi,
I am about to start on Cycle Accurate C Modelling for some Hardware
modules.
I searched in google. Got some info. Any Pointers or Help in this
regard is appreciated.
Thanks,
Be Well

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Modelling an oscillator using Verilog AMS [email protected] Verilog 0 01-04-2006 09:16 PM
Anyone can tell me the difference between the behavorial modelling and RTL modelling? reffud Verilog 1 06-29-2005 07:20 AM
need help in modelling [email protected] Verilog 1 01-17-2005 02:07 PM
need help in modelling [email protected] Verilog 1 01-17-2005 09:40 AM
generate a 20 MHZ clock(pulse) with duty cycle other than 50 % from master clock 40 MHZ having 50 % duty cycle MegaPowerStar Verilog 2 08-19-2003 02:29 AM


All times are GMT +1. The time now is 02:19 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved