FPGA Central

I have a hierarchical gate-level verilog netlist. That is, it contains
modules, which are instanced in other modules, etc. I need a flat
gate-level verilog netlist (one module, with just the logic gates). Is
there a free tool to do this? I don't have access to digital design
tools because, as the subject line says, I am an analog designer.

The hierarchical netlist was generated from a hierarchical Cadence
schematic, so if someone knows how to convince Cadence analog artist to
generate a flat gate-level verilog netlist (4.4.6 or 5.0 Cadence) that
is just as good or better.

Thanks in advance,
Jackson Harvey