FPGA Central

Hi,

Kindly clarify the following doubts on Two FF synchronizer.
Most of the material available in net says the two flip-flop
synchronizer is sufficient to remove all likely metastability.

The first flip-flop samples the asynchronous input signal and waits
for a full clock cycle to permit any metastability output signal to
come to stable either 1 or 0.

How can the ouput of the first FF will becomes stable before the
next clock cycle? On what factors it will depend?
(Theoritically it not guarenteed that Two FF synchronizer avoids
metastability but proctically it is, how?)

Whats vendors approach for the first FF to go to stable state before
next sampling edge arrives?
Whats information/insructions the vendor can provide designers
regarding first FF settling time etc....?

What are all the options available in the designer hand to make the
two ff synchronizer work properly?

Please make me clear.

Thanks in advance.

Regards,
SruthiTeja.

"himassk" <[email protected]> writes:

> Hi,
>
> Kindly clarify the following doubts on Two FF synchronizer.
> Most of the material available in net says the two flip-flop
> synchronizer is sufficient to remove all likely metastability.
>
> The first flip-flop samples the asynchronous input signal and waits
> for a full clock cycle to permit any metastability output signal to
> come to stable either 1 or 0.
>
> How can the ouput of the first FF will becomes stable before the
> next clock cycle? On what factors it will depend?
> (Theoritically it not guarenteed that Two FF synchronizer avoids
> metastability but proctically it is, how?)
>
> Whats vendors approach for the first FF to go to stable state before
> next sampling edge arrives?
> Whats information/insructions the vendor can provide designers
> regarding first FF settling time etc....?

This app note from Philips discuss the metastability quite well.
http://www.semiconductors.philips.co...es/AN219_1.pdf


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>