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I am doing 16 to 32 bit sign extention like below. I tested it out
and it works great. I know it is just 2 assign statements, but I am
wondering if there is a better way of doing this..

module sign_extender(in, out);
input [15:0] in;
output [31:0] out;
assign out[31:16] = {16{in[15]}};
assign out[15:0] = in[15:0];
endmodule

Mahurshi Akilla

On 22 Apr 2007 10:51:18 -0700, Mahurshi Akilla <[email protected]>
wrote:

>I am doing 16 to 32 bit sign extention like below. I tested it out
>and it works great. I know it is just 2 assign statements, but I am
>wondering if there is a better way of doing this..
>
>module sign_extender(in, out);
>input [15:0] in;
>output [31:0] out;
> assign out[31:16] = {16{in[15]}};
> assign out[15:0] = in[15:0];
>endmodule

Yes, there is. Use Verilog-2001 signed arithmetic.

module sign_extender (
input signed [15:0] in,
output signed [31:0] out);

assign out = in; // sign-extends

endmodule

Indeed, because of the Verilog-2001 signed arithmetic
features, you probably don't need the sign_extender
module at all. You can simply use signed arithmetic
wherever you need it.

NOTE VERY CAREFULLY, however, that sign extension
works only if EVERY operand in an arithmetic expression
is signed. If there is ANY unsigned operand in the
expression, then the WHOLE expression is evaluated in
traditional Verilog-95 unsigned fashion, without sign
extension. A big Gotcha!.
--
Jonathan Bromley, Consultant

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On Apr 22, 10:51 am, Mahurshi Akilla <mahur...@gmail.com> wrote:
> I am doing 16 to 32 bit sign extention like below. I tested it out
> and it works great. I know it is just 2 assign statements, but I am
> wondering if there is a better way of doing this..
>
> module sign_extender(in, out);
> input [15:0] in;
> output [31:0] out;
> assign out[31:16] = {16{in[15]}};
> assign out[15:0] = in[15:0];
> endmodule
>
> Mahurshi Akilla

assign out = { {16{in[15]}, in[15:0] };

On 22 Apr 2007 10:51:18 -0700, Mahurshi Akilla <[email protected]>
wrote:

>I am doing 16 to 32 bit sign extention like below. I tested it out
>and it works great. I know it is just 2 assign statements, but I am
>wondering if there is a better way of doing this..
>
>module sign_extender(in, out);
>input [15:0] in;
>output [31:0] out;
> assign out[31:16] = {16{in[15]}};
> assign out[15:0] = in[15:0];
>endmodule

assign out = {{16{in[15]}}, in[15:0]};