FPGA Central

Designing for high-speed serial links?

Attend Altera's free, practical workshop to learn important silicon, board, and system solutions you'll need to design for high-speed serial links at your desired bit-error rate. Test drive our systems through a hands-on signal integrity tutorial with real silicon and design exercises.

Special presentation by Dr. Eric Bogatin
Title: Impact of Return Current Discontinuities on 10 Gbps High Speed Serial Links

You'll also learn:
-High-speed channel design techniques and guidelines for optimal transceiver signal integrity.
-The impact of power distribution networks (PDN) and decoupling strategies.
-System design solutions, including power design tradeoffs, transceiver simulations and high speed measurement techniques.
-Protocol offerings including PCI Express.
-The breakdown of jitter and its impact on your system.

Where: Altera HQ, 101 Innovation Dr, San Jose 95134
When: Thursday, April 2, 2009 - 8:30am
Contact: Salman Jiva, sjiva (AT) altera (DOT) com
Registration: http://www.altera.com/sjworkshop
Sign up today, as space is limited. Lunch will be provided.

Partners include:
Arrow
Cadence
Linear Technologies
Mentor Graphics
Octera Solutions
Tektronix

Salman Jiva
Altera Corporation
Technical Marketing Manager
High End FPGAs


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