FPGA Central

Hello SI-Listers,
I have a position open for an experienced signal integrity engineer in our organization.

Location is San Jose, CA area, and position if available immediately.

This is a prviate company, and I the hiring manager and this is not a "headhunter" or HR department.
I apologize for the anonymous post but we are in stealth mode.

The position is for design and SI for IC package and PCB design, with focus on package signal and power-integrity.
Familiarity with Wirebond PBGA and* Flip-Chip (HDBU/Ceramic) IC package technologies is preferred.

Requirements are 3years MSEE, or 5years BSEE.

Experience with Sigrity (PowerSI/SpeedSIM), Ansoft HFSS, Agilent ADS/Momentum, HSpice, and Cadence APD/Allegro/SpecctraQuest
will receive extra consideration.
Experience with at least two simulation/modeling*tools is required.

Understanding of SerDes (PCIe Gen1/Gen2, XAUI, XFI, SATA, etc) and DDR2/DDR3, and other parallel interface standards is a must.

Serious candidates only please.
Thank you.
Please reply to bayarea_siguy (AT) yahoo (DOT) com



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