FPGA Central

We are looking for a senior signal integrity engineer/manager with package
design background to join Global Unichip located in San Jose, CA. Job
description is given below. If you are interested, please send me your
resume or contact me directly:

Thanks.
Larry Zu
Director of Engineering Management & Business Development
Global Unichip Corp.
2595 Junction Ave.
San Jose, CA 95134
408-382-8907 (O)

__________________________________________________ ________

JOB DESCRIPTION FOR SIGNAL INTEGRITY ENGINEER

An experienced signal integrity engineer to design and analyze high speed
interfaces and power distribution network for flip-chip package. The
successful candidate will work with our US customers and our Taiwan
package design team to define and design a package to meet high power and
high speed requirements. As a chip and package design company, the
individual will be part of a larger team with system architects, logic
designers, ASIC engineers, and SI engineers.

Responsibilities:
1). Work with US customers and GUC chip designers to define a packaging
solution.
2). Supervise GUC signal integrity engineers to conduct power and signal
integrity analysis.
3). Work with GUC substrate designer and package design engineer to come
up with a cost effective package.

Detailed electrical analysis are listed below:
1). Power integrity analysis for each PWR/GND domain: Extract package
parasitic R/L/C or S parameters.
Run SPICE simulation to meet Si Vddmin spec. Decoupling strategy
and analysis.
2). Simultaneous switching noise/output (SSN or SSO) analysis for each
I/O PWR/GND domain.
3). Flip-chip bump or wirebond pad re-arrangement for chip-package-board
co-design.
4). Optimal layer stackup & PWR/GND plane/island assignment to minimize
voltage drop/noise/coupling.
5). Special noise-sensitive power supply analysis and layout watch.
Example: PLL
6). Bus trace length matching and impact to timing.
7). Crosstalk analysis and reduction.
8). Impedance control for single ended and differential signals.
9). Insertion loss and return loss modeling and improvement with HFSS.
10).Timing analysis.
11).High speed I/O package design for PCI-E I & II, XAUI, 10G SerDes, FSB,
DDR I, II, and III
12).EMI reduction and shielding techniques.

Requirement:
MSEE/CS with 5-10 years of experience, or BSEE/CS with 7-10+ years
experience.
Proficiency with SPICE circuit simulation, field-solver and time/frequency
domain analysis.
Familiar with high speed SerDes design, PLL design, LVDS, CML and other
high-performance I/O interconnects.
Solid background on transmission line theory and in depth knowledge of
electromagnetics is a plus.
Experience with HSPICE, HFSS, Si-Wave, Paksi-E, and Agilent ADS.
Experience with lab measurements using oscilloscopes, TDRs, VNAs, and
spectrum analyzers.
Self motivated, teamwork, and good communication skills.
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