FPGA Central

Hi SI people,


Can someone offer an explanation how a SERDES CDR can recover data with an asynchronous reference clock? Example is PCI-Express (reference PCI EXPRESS BASE SPECIFICATION, REV 2.1 section 4.3.7.5. "Separate Refclk Architecture"), where Refclk #1 drives the TX circuit and Refclk #2 drives the RX circuit. How does this CDR circuit work? I thought that even if they were separate clocks they'd have to be frequency locked, and a PCI-SIG presentation indicates they can be +/-300ppm each.



Thanks,



Ivor Bowden


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Ivor, the receive CDR phase locks onto the incoming data stream and
dumps the data into an elastic store: FIFO. The Rx clock controls data
transfer after buffered CDR. Channel utilization is under 100% by more
than 2X the clock tolerance. Therefore a transmit stream will never
exceed the receiving end's ability to absorb the data.

Steve.
Bowden, Ivor wrote:
> Hi SI people,
>
>
> Can someone offer an explanation how a SERDES CDR can recover data with an asynchronous reference clock? Example is PCI-Express (reference PCI EXPRESS BASE SPECIFICATION, REV 2.1 section 4.3.7.5. "Separate Refclk Architecture"), where Refclk #1 drives the TX circuit and Refclk #2 drives the RX circuit. How does this CDR circuit work? I thought that even if they were separate clocks they'd have to be frequency locked, and a PCI-SIG presentation indicates they can be +/-300ppm each.
>
>
>
> Thanks,
>
>
>
> Ivor Bowden
>
>
> __________________________________________________ _____________________
> This e-mail and any files transmitted with it are proprietary and intended solely for the use of the individual or entity to whom they are addressed. If you have reason to believe that you have received this e-mail in error, please notify the sender and destroy this email and any attached files. Please note that any views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the Curtiss-Wright Corporation or any of its subsidiaries. Documents attached hereto may contain technology subject to government export regulations. Recipient is solely responsible for ensuring that any re-export, transfer or disclosure of this information is in accordance with applicable government export regulations. The recipient should check this e-mail and any attachments for the presence of viruses. Curtiss-Wright Corporation and its subsidiaries accept no liability for any damage caused by any virus transmitted by this e-mail.
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>
>
>
>


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Thank you Steve! Please let me reiterate to make sure I understand you.

"The Rx clock controls data transfer AFTER buffered CDR" is the key thing I was missing, the CDR will always have a PLL or some other type of clock regeneration recovered from the RX data stream.

In addition, to quote an off list reply I received (thanks Leonard) "When there is no data or no lock the internal PLL will normally frequency/ phase lock onto the reference clock".

Is this summary of the three PCIE RX clock architectures correct:

Common Clock
The host transmits a common reference clock (RefClk) that is used by the downstream device e.g. ExpressModule for both TX and RX. The downstream device has a PLL that is frequency locked to the RefClk and phase locked to the RX data.

Data Clock
It is not necessary to have a common reference clock. The downstream device has a PLL that is frequency and phased phase locked to the RX data. This clock could also be used by the downstream device for TX, or it could use a separate TX clock within 600ppm of the RX clock.

Separate Clock
It is not necessary to have a common reference clock. The downstream device has a PLL that is frequency and phased phase locked to the RX data. This clock could also be used by the downstream device for TX, or it could have a separate TX clock within 600ppm of the RX clock. In the absence of data, the RX clock is locked to the local reference clock.

?

Noted that (per Leonard) "There are many other ways to perform asynchronous sampling in the digital domain", so the each above summary method would just be one (typical?) way.

Comments welcome.

Thanks,

Ivor

-----Original Message-----
From: steve weir [mailto:weirsi (AT) ipblox (DOT) com]
Sent: Thursday, December 10, 2009 12:43 AM
To: Bowden, Ivor
Cc: si-list (AT) freelists (DOT) org
Subject: Re: [SI-LIST] SERDES CDR with asynchronous reference clock?

Ivor, the receive CDR phase locks onto the incoming data stream and dumps the data into an elastic store: FIFO. The Rx clock controls data transfer after buffered CDR. Channel utilization is under 100% by more than 2X the clock tolerance. Therefore a transmit stream will never exceed the receiving end's ability to absorb the data.

Steve.
Bowden, Ivor wrote:
> Hi SI people,
>
>
> Can someone offer an explanation how a SERDES CDR can recover data with an asynchronous reference clock? Example is PCI-Express (reference PCI EXPRESS BASE SPECIFICATION, REV 2.1 section 4.3.7.5. "Separate Refclk Architecture"), where Refclk #1 drives the TX circuit and Refclk #2 drives the RX circuit. How does this CDR circuit work? I thought that even if they were separate clocks they'd have to be frequency locked, and a PCI-SIG presentation indicates they can be +/-300ppm each.
>
>
>
> Thanks,
>
>
>
> Ivor Bowden
>
>
> __________________________________________________ ____________________
> _ This e-mail and any files transmitted with it are proprietary and
> intended solely for the use of the individual or entity to whom they are addressed. If you have reason to believe that you have received this e-mail in error, please notify the sender and destroy this email and any attached files. Please note that any views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the Curtiss-Wright Corporation or any of its subsidiaries. Documents attached hereto may contain technology subject to government export regulations. Recipient is solely responsible for ensuring that any re-export, transfer or disclosure of this information is in accordance with applicable government export regulations. The recipient should check this e-mail and any attachments for the presence of viruses. Curtiss-Wright Corporation and its subsidiaries accept no liability for any damage caused by any virus transmitted by this e-mail.
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
>
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



__________________________________________________ _____________________
This e-mail and any files transmitted with it are proprietary and intended solely for the use of the individual or entity to whom they are addressed. If you have reason to believe that you have received this e-mail in error, please notify the sender and destroy this email and any attached files. Please note that any views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the Curtiss-Wright Corporation or any of its subsidiaries. Documents attached hereto may contain technology subject to government export regulations. Recipient is solely responsible for ensuring that any re-export, transfer or disclosure of this information is in accordance with applicable government export regulations. The recipient should check this e-mail and any attachments for the presence of viruses. Curtiss-Wright Corporation and its subsidiaries accept no liability for any damage caused by any virus transmitted by this e-mail.
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Ivor, yes that is pretty much it. When the channel detects data loss,
the VCO locks to the local clock in order to reduce lock time when data
reappears. As long as each transmitter operates within the absolute
clock tolerance the channel works. Ethernet has worked this way for a
long time. The disadvantage of distributing clocks through trees is
jitter accumulation.

Steve.
Bowden, Ivor wrote:
> Thank you Steve! Please let me reiterate to make sure I understand you.
>
> "The Rx clock controls data transfer AFTER buffered CDR" is the key thing I was missing, the CDR will always have a PLL or some other type of clock regeneration recovered from the RX data stream.
>
> In addition, to quote an off list reply I received (thanks Leonard) "When there is no data or no lock the internal PLL will normally frequency/ phase lock onto the reference clock".
>
> Is this summary of the three PCIE RX clock architectures correct:
>
> Common Clock
> The host transmits a common reference clock (RefClk) that is used by the downstream device e.g. ExpressModule for both TX and RX. The downstream device has a PLL that is frequency locked to the RefClk and phase locked to the RX data.
>
> Data Clock
> It is not necessary to have a common reference clock. The downstream device has a PLL that is frequency and phased phase locked to the RX data. This clock could also be used by the downstream device for TX, or it could use a separate TX clock within 600ppm of the RX clock.
>
> Separate Clock
> It is not necessary to have a common reference clock. The downstream device has a PLL that is frequency and phased phase locked to the RX data. This clock could also be used by the downstream device for TX, or it could have a separate TX clock within 600ppm of the RX clock. In the absence of data, the RX clock is locked to the local reference clock.
>
> ?
>
> Noted that (per Leonard) "There are many other ways to perform asynchronous sampling in the digital domain", so the each above summary method would just be one (typical?) way.
>
> Comments welcome.
>
> Thanks,
>
> Ivor
>
> -----Original Message-----
> From: steve weir [mailto:weirsi (AT) ipblox (DOT) com]
> Sent: Thursday, December 10, 2009 12:43 AM
> To: Bowden, Ivor
> Cc: si-list (AT) freelists (DOT) org
> Subject: Re: [SI-LIST] SERDES CDR with asynchronous reference clock?
>
> Ivor, the receive CDR phase locks onto the incoming data stream and dumps the data into an elastic store: FIFO. The Rx clock controls data transfer after buffered CDR. Channel utilization is under 100% by more than 2X the clock tolerance. Therefore a transmit stream will never exceed the receiving end's ability to absorb the data.
>
> Steve.
> Bowden, Ivor wrote:
>
>> Hi SI people,
>>
>>
>> Can someone offer an explanation how a SERDES CDR can recover data with an asynchronous reference clock? Example is PCI-Express (reference PCI EXPRESS BASE SPECIFICATION, REV 2.1 section 4.3.7.5. "Separate Refclk Architecture"), where Refclk #1 drives the TX circuit and Refclk #2 drives the RX circuit. How does this CDR circuit work? I thought that even if they were separate clocks they'd have to be frequency locked, and a PCI-SIG presentation indicates they can be +/-300ppm each.
>>
>>
>>
>> Thanks,
>>
>>
>>
>> Ivor Bowden
>>
>>
>> __________________________________________________ ____________________
>> _ This e-mail and any files transmitted with it are proprietary and
>> intended solely for the use of the individual or entity to whom they are addressed. If you have reason to believe that you have received this e-mail in error, please notify the sender and destroy this email and any attached files. Please note that any views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the Curtiss-Wright Corporation or any of its subsidiaries. Documents attached hereto may contain technology subject to government export regulations. Recipient is solely responsible for ensuring that any re-export, transfer or disclosure of this information is in accordance with applicable government export regulations. The recipient should check this e-mail and any attachments for the presence of viruses. Curtiss-Wright Corporation and its subsidiaries accept no liability for any damage caused by any virus transmitted by this e-mail.
>> ------------------------------------------------------------------
>> To unsubscribe from si-list:
>> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>>
>> or to administer your membership from a web page, go to:
>> http://www.freelists.org/webpage/si-list
>>
>> For help:
>> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>>
>>
>> List technical documents are available at:
>> http://www.si-list.net
>>
>> List archives are viewable at:
>> http://www.freelists.org/archives/si-list
>>
>> Old (prior to June 6, 2001) list archives are viewable at:
>> http://www.qsl.net/wb6tpu
>>
>>
>>
>>
>>
>
>
>
> __________________________________________________ _____________________
> This e-mail and any files transmitted with it are proprietary and intended solely for the use of the individual or entity to whom they are addressed. If you have reason to believe that you have received this e-mail in error, please notify the sender and destroy this email and any attached files. Please note that any views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the Curtiss-Wright Corporation or any of its subsidiaries. Documents attached hereto may contain technology subject to government export regulations. Recipient is solely responsible for ensuring that any re-export, transfer or disclosure of this information is in accordance with applicable government export regulations. The recipient should check this e-mail and any attachments for the presence of viruses. Curtiss-Wright Corporation and its subsidiaries accept no liability for any damage caused by any virus transmitted by this e-mail.
>
>


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Old (prior to June 6, 2001) list archives are viewable at:
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