FPGA Central

Hi,
the number of layers is of no direct importance. The main factors are

- trace width (determines skin loss)
- dielectric material (determines dielectric loss tangent)
- trace configuration (stipline, microstrip, CPW)
- via parasitics
- driver and receiver noise
- do transmitter/receiver use some sort of pre-emphasis or de-emphasis

As a VERY ROUGH starting point - please don't bet your company's future on
it without verifying with a decent simulation tool - in a 4mil wide
stripline trace in FR-4, neglecting via parasitics, and assuming no
pre-emphasis, for a data rate of 2.5 GB/s, you can go approx. 20 inches
before the data eye closes too much.

For a first order approximation - so you can get a rough feeling of where
your actual design is - there is a very nice web-based tool (freeware!) by
Tom Clupper that allows you to play with all these parameters (including
pre-emphasis and rough via models) and look at the data eye, TDR response,
frequency response etc of your path:

http://www.tlinesim.com/

Hope that gets you going

Wolfgang








Mashook Ahamed Usman <MashookAhamed.Usman (AT) aricent (DOT) com>
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11/18/2009 04:00 AM

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[SI-LIST] Maximum length of 2.5G SerDes trace






Hi,
It would be useful if I know the maximum length of 2.5G SerDes trace that
can travel in a 14 layer board in which the reference plane(Ground) is
adjacent to it.
Thank you very much,
Mashook Usman
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