FPGA Central

Hi Girish--
There really aren't routing guidelines for carrier cards for PCI-X since
topologies for the bus can vary so widely, since it is typically a
multi-drop bus. The add-on cards have specs so that they are a fixed
entity around which you can design your carrier card.
This also brings up an important issue about looking at "delay" versus
length. Especially for a bus like PCI-X which employs common-clock
timing, calculating accurate "flight times" for your signals is
especially important. Flight times include the effects of loading of
the receiver and effects of reflections from connectors, vias, etc. in
addition to the interconnect delay. Flight times are also correlated to
the internal chip timing (in this case Tco) so you can make sure you are
meeting your complete system timing. Once you have calculated the min
and max flight times for your signals to meet your setup and hold
requirements, you can test different routing lengths in simulation to
see what length range meets your flight time requirements.
It will be a little easier for you if you are just doing a
point-to-point PCI-X 133 interface, which is the most common. (Although
if I remember correctly, you can make a multi-drop PCI-X 133 interface
work with careful planning). When calculating timing, you can also add
in some extra margin for things like crosstalk and jitter. Although the
more effects you actually include in your simulation, the less you have
to guess at how much margin to add.

There is a recorded webinar on PCI-X design avilable at
www.mentor.com/hyperlynx if you click on Multimedia and go to the last
page.
Or the direct link, which is kind of long, is:
http://www.mentor.com/products/pcb-s...a/overview/tra
de-offs-in-pci-x-interconnect-design-912ee4dd-6beb-4e84-8479-a7a7143b7d8
8

The presentation is based on our PCI-X Design Kit.

--Pat


Patrick Carrier
Technical Marketing Engineer
High Speed Design
Mentor Graphics Corporation
Patrick_Carrier (AT) mentor (DOT) com
ph. (512) 425-3015


-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On Behalf Of Girish Gopi
Sent: Thursday, July 02, 2009 5:22 AM
To: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] max. & min. routing lengh of PCI X133Mhz

Hi there,
I am using the PCIe to PCI-X bridge (P17C9X130DNDE from pericom).

http://www.pericom.com/pdf/databriefs/PI7C9X130_db.pdf

I am unable to findout the routing guidelines for the PCI-X 133MHz
signal in the carrier card. PCI-X spec and other documents what ever i
refered has only routing guidelines for the add on cards. Is there any
recommendation for the min and max trace length for the carrier card
PCI-X 133MHz? How to calculate the min and max trace length?

Thanks in advance
Girish Gopi
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