FPGA Central

hi
you have to do timing analysis on the bus, based on datasheet parameters (input setup/hold), PCB trace lengths chip-to-chip and SI-simulations with proper IBIS models (to get the signal rise times at given number of chip-loads and given trace capacitances and signal reflections ).
The signals have to arrive early enough to meet the input setup requirements (max length), and late enough to meet the input hold requirements (min length) of the actual receiver chip. obviously do it between each initiator-target pair. In the signal arrival time, the load-based rise time, the PCB propagation delay, the clock network skew and the driver chip output (clock to output delay, min/max) parameters have role. so you get min/max arrival times, and these have to meet your input hold/setup requirements.
check this calculator for min/max PCB lengths and for max frequency:
http://www.buenos.extra.hu/iromanyok...g_analysis.xls
(synchronous-pre-layout tab. use internet explorer)

Istvan Nagy
CCT


Girish Gopi <girish.gopi (AT) datapatterns (DOT) co.in> wrote:


> Hi there,
> I am using the PCIe to PCI-X bridge (P17C9X130DNDE from pericom).
>
> http://www.pericom.com/pdf/databriefs/PI7C9X130_db.pdf
>
> I am unable to findout the routing guidelines for the PCI-X 133MHz signal in the carrier card. PCI-X spec and other documents what ever i refered has only routing guidelines for the add on cards. Is there any recommendation for the min and max trace length for the carrier card PCI-X 133MHz? How to calculate the min and max trace length?
>
> Thanks in advance
> Girish Gopi
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