FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > Mailing List > si-list

si-list si-list mailer

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 02-13-2009, 08:20 AM
navaram kumar
Guest
 
Posts: n/a
Default [SI-LIST] Fatal error: DCtrCurv: source / resistor not in circuit

Hi all
I am using ngspice it got this fallowing error for CS amplifier


*CS Amplifier


M2 2 1 2 0 NFET W=150n L=130N


M1 2 3 0 0 nfet W=150N L=130N




Vin 3 0 SIN(.6 .01 10kHz 0NS .0001)

*Vin 3 4 AC 1

..dc
..op
vdd 1 0 1.2


..tran 100n 100u



this is the above netlist using tsmc 130nm perameters

plese slove my probem

Thanks
Navaram


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request (AT) freelists (DOT) org with 'help' in the Subject field


List technical documents are available at:
http://www.si-list.net

List archives are viewable at:
http://www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Fatal Error ISE 9.1 [email protected] FPGA 2 08-01-2007 07:30 PM
ise 9.2 fatal error dude FPGA 1 07-25-2007 06:49 PM
ModelSim Error : "Fatal error in Process determine_phase_shift" during post synthesis of Xilinx vhd fpgaengineer VHDL 7 03-12-2007 09:24 PM
FATAL ERROR IN EDK 7.1i savs FPGA 1 07-07-2006 06:24 PM
ISE 6.1 - Fatal Error ANANTHARAJ.T.V. FPGA 1 05-30-2005 02:09 PM


All times are GMT +1. The time now is 03:54 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved