FPGA Central

Technical Paper Newsletter 4-29-2009 Tech Paper Library Home  NEW FEATURED TECHNICAL PAPERS Collective "Green" Wisdom: Environmental initiatives evoke unprecedented power of multifunctional collaboration
Kimberly Allen and Pamela J. Gordon • Technology Forecasters
Name an organization comprising more than 10 people in which all functions work seamlessly together. Few corporations are brilliant at rising above the agendas held by diverse disciplines, departments, and regions to achieve overarching goals.
Fastboot Techniques for the x86 Architecture
Ben Biron • QNX Software Systems
This paper explores factors that affect boot time and discusses the dramatic boot-time and performance gains that result from replacing the BIOS with customized early initialization of peripherals.
Timing Closure Exploration Tools with SmartXplorer and PlanAhead
Xilinx
Timing closure is one of the most challenging aspects in modern FPGA design. It is difficult to avoid this challenge when the complexity of FPGA devices doubles every 1½ years and when designers try to pack more and more functionality into a single chip.
The Integration Imperative—When the Whole is Greater than the Sum of Parts
Graham Teague • TriQuint Semiconductor
In the highly competitive mobile handset business, manufacturers face continuous pressure to deliver sleek form factors with ever more functionality in increasingly compressed time frames.
Secure by Design: Using a Microkernel RTOS to Build Secure, Fault-Tolerant Systems
Paul Leroux • QNX Software Systems
To thwart such attacks, many companies and organizations surround their systems with a protective barrier that consists of network security, cryptographic security, and even physical security.
Understanding Metastability in FPGAs
Altera
This white paper describes metastability in FPGAs, why it happens, and how it can cause design failures. It explains how metastability MTBF is calculated, and highlights how various device and design parameters affect the result.
 HIDDEN GEMS DO-254 Compliance: Reducing Project Cost by Avoiding Common Pitfalls
Tammy Reeve and Michelle Lange • Mentor Graphics

Crest Factor Reduction for OFDM-Based Wireless Systems
Altera

Power Supply Measurement and Analysis
Tektronix

TrustMe-ViP: A Virtual RF System Platform Project for TPD
Gilles Jacquemod • Mentor Graphics

A New Approach to FPGA Testing and Validation for Today's Market
DAFCA

 WHAT'S HOT The Top 10 Issues that Cause Bad Prototypes
Screaming Circuits

Spot and avoid the counterfeit component traps
M. Simard-Normandin • MuAnalysis

Controller Area Network (CAN) Basics
Keith Pazul • Microchip Technology

High-Definition Surveillance Systems Using Low Cost FPGAs
Suhel Dhanani • Altera

JTAG Debug—Everything You Need to Know
Mentor Graphics


CAN Primer: Creating your own Network
Robert Boys • Keil, an ARM Company

Fundamentals of Signal Integrity
Tektronix

Go Beyond Compliance for Profitability and Environmental Sustainability
ENOVIA, a Dassault Systèmes Brand

Reducing Physical Verification Cycle Time
John Ferguson • Mentor Graphics

Low-Power RF Guide
Texas Instruments

HDI Layer Stackups for Large Dense PCBs
Mentor Graphics

Environmental Friendly Protection of Automotive Electronics
Kent Larson • Dow Corning Electronics

Effective Stackup Design for High-speed Interfaces
Mentor Graphics

Dow Corning material and application center prove key to prototyping of automotive starter/alternator design
Dow Corning Electronics

Demystifying DO-254
Tom Dewey • Mentor Graphics

Coordinated Circuit Protection Helps Manufacturers Meet Requirements of GR-1089-CORE, Issue 4
Tyco Electronics

Advanced Dynamic Power Reduction Techniques: Operand Isolation, Operand Pre-computation, and Multi-VDD
Kajin Shi and Neel Desai • Synopsys

Measuring the Performance of Equalized Serial Data Links Across the Design Flow
Steven McKinney et al • Mentor Graphics and Tektronix

Overcoming LTE PHY Design Challenges Using ESL Design Methodologies
Louie Valeña • CoWare

Establishing Confidence in PDN Simulation
Eric Bogatin • Bogatin Enterprises

Nucleus Platform Solutions
Mentor Graphics

Solving FM Antenna Design Challenges in Portable Devices
Natalian Zhai • Silicon Laboratories

The PSP Model in RF CMOS Design
Fujitsu Microelectronics

An Evolution of Gate and Via Parasitic Resistance Extraction
Jarrod Stykes • Cypress Semiconductor

Migrating Legacy RTOS Device Drivers to Embedded Linux
Bill Weinberg • MontaVista Software

MSP430 Ultra-Low-Power Microcontrollers
Texas Instruments

Simplifying BLDC Commutation and Feedback System
Teng and Kong Leong • Avago Technologies

Power Integrity Effects of High Density
Happy Holden and Patrick Carrier • Mentor Graphics

Xilinx Virtex-5 (UMC 65nm Process) FPGA (XC5VLX50)
Semiconductor Insights

HDI Layer Stackups for Large Dense PCBs
Mentor Graphics

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