FPGA Central

Technical Paper Newsletter 4-15-2009 Tech Paper Library Home  NEW FEATURED TECHNICAL PAPERS Measuring the Performance of Equalized Serial Data Links Across the Design Flow
Steven McKinney et al • Mentor Graphics and Tektronix
In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.
Overcoming LTE PHY Design Challenges Using ESL Design Methodologies
Louie Valeña • CoWare
The 3rd Generation Partnership Project (3GPP) announced the functional freeze of the LTE specs (Release 8) in Dec 2008, but even before that, Nokia Siemens Networks had already announced the availability of LTE base stations and LG had announced LTE baseband chips for the handset.
JTAG Debug—Everything You Need to Know
Mentor Graphics
This paper explains the issues and concepts that require a JTAG connection and how it provides much needed visibility and control of a modern processor core-based system.
Establishing Confidence in PDN Simulation
Eric Bogatin • Bogatin Enterprises
This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.
CAN Primer: Creating your own Network
Robert Boys • Keil, an ARM Company
CAN is extensively used in automobiles and trucks but has found applications everywhere. There are many "application" layers available for CAN such as ISO 15765 (cars), J1939 (trucks) and CANopen (factory automation) but it is very easy to develop your own protocol that will fit and simplify your needs.
Tiny High Efficiency 2A Buck Regulator Directly Accepts Automotive, Industrial and Other Wide Ranging Inputs
Kevin Huang • Linear Technology
The LT3480 is a new step-down regulator that accepts input from up to 38V (60V transient) while providing excellent line and load regulation and dynamic response. The LT3480 offers high efficiency solutions over wide load range and keeps the output ripple low during Burst Mode operation.
Reducing Physical Verification Cycle Time
John Ferguson • Mentor Graphics
This paper discusses Calibre, which provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations.
Go Beyond Compliance for Profitability and Environmental Sustainability
ENOVIA, a Dassault Systèmes Brand
This white paper addresses how a PLM strategy helps companies achieve profitability targets while meeting global compliance regulations and helping the environment.
Electro-Migration Check with Eldo
Alfredo Tomasini • Linear Technology
The scope of this paper is to introduce some techniques that make the electro-migration check part of the standard post-layout simulation flow by eliminating the side effect of post-simulation to make it scalable with the design and easy to implement in any technology.
Nucleus Platform Solutions
Mentor Graphics
Electronic devices are evolving at a breakneck pace as manufacturers strive to differentiate from the crowd with more features, lower power consumption, and a better user experience. Learn how Mentor Graphics is addressing this issue with their Nucleus Platform Solutions.
 HIDDEN GEMS COT Drivers Control LED Ripple Current
Chris Richardson • National Semiconductor

Battery Management Design for High Power Lithium Battery Stacks
Greg Zimmer • Linear Technology

Coordinated Circuit Protection Helps Manufacturers Meet Requirements of GR-1089-CORE, Issue 4
Tyco Electronics

Advanced Dynamic Power Reduction Techniques: Operand Isolation, Operand Pre-computation, and Multi-VDD
Kajin Shi and Neel Desai • Synopsys

Analog IC Design with Low-Dropout Regulators (part 1 of 5)
Gabriel Alfonso Rincón-Mora • Georgia Institute of Technology

 WHAT'S HOT Choosing between pipeline vs. sigma delta ADCs for communications applications
Noel O'Riordan • Silicon & Software Systems

Fundamentals of Signal Integrity
Tektronix

Wireless triangulation using RSSI signals
Michael Harney

High-Definition Surveillance Systems Using Low Cost FPGAs
Suhel Dhanani • Altera

Ways to Use USB in Embedded Systems
Yingbo Hu and Ralph Moore • Micro Digital


Solving FM Antenna Design Challenges in Portable Devices
Natalian Zhai • Silicon Laboratories

Wind River High-Assurance Solutions for Aerospace and Defense
Wind River

The PSP Model in RF CMOS Design
Fujitsu Microelectronics

Introducing the Xilinx Targeted Design Platform: Fulfilling the Programmable Imperative
Tim Erjavec • Xilinx

An Evolution of Gate and Via Parasitic Resistance Extraction
Jarrod Stykes • Cypress Semiconductor

Migrating Legacy RTOS Device Drivers to Embedded Linux
Bill Weinberg • MontaVista Software

MSP430 Ultra-Low-Power Microcontrollers
Texas Instruments

Raising the RTL Abstraction Level and Design Conciseness with SystemVerilog
Sachin Kakkar et al • Mentor Graphics

Isolated Supply Overview and Design Trade-Offs
David Baba • National Semiconductor

Simplifying BLDC Commutation and Feedback System
Teng and Kong Leong • Avago Technologies

Power Integrity Effects of High Density
Happy Holden and Patrick Carrier • Mentor Graphics

Introduction to Secure Processing
CPU Tech

50 V RF LDMOS: An Ideal RF Power Technology for ISM, Broadcast and Radar Applications
Pierre Piel et al • Freescale Semiconductor

Power Management in an Embedded Multiprocessor Cluster
Matthias Knoth • MIPS Technologies

Automotive Isolation Amplifier for Voltage Sensing
Kenji Yamamoto and Andy Poh • Avago Technologies

Xilinx Virtex-5 (UMC 65nm Process) FPGA (XC5VLX50)
Semiconductor Insights

Next Generation Secure Mobile Devices
David Kleidermacher • Green Hills Software

Embedded Design Techniques for Developing Cost-Effective Communications
Tektronix

Mitigation Methods for Parasitic Turn-On Effect Due to Miller Capacitor
Avago

HDI Layer Stackups for Large Dense PCBs
Mentor Graphics

  Around the Network
Live Webinar Calendar
Electronics Company Directory
TechOnline University Courses
Under the Hood Teardowns
VirtuaLab Product Evaluation
Follow Tech Papers on Twitter

About This E-Mail. TechOnline respects your time and privacy. If you are not interested in receiving future newsletters on this subject, click here.

**PLEASE NOTE** You are currently subscribed under the e-mail address

newsletter (AT) list (DOT) fpgacentral.com

You must use this address when trying to unsubscribe.



Technical Paper Submissions
Click here to submit your paper to TechOnline's
Technical Paper Library.

You may view our privacy statement here.

Pass It On.... Please feel free to forward this newsletter to your colleagues.




Copyright © UNITED BUSINESS MEDIA Limited
Ludgate House
245 Blackfriars Road
London, UK SE1 9UY