FPGA Central

VERIFICATION HORIZONS
A QUARTERLY PUBLICATION OF MENTOR GRAPHICS Q1 '09 - VOL.
5, ISSUE 1

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Hello

As I sat down to write this note to you, I was thinking of
the recent ice storms we have had here in the NE as a
metaphor for the economic downturn we've been experiencing.
The current economic climate is as inhospitable as a New
England winter, so to survive we have to "bundle up" and
try to keep warm. In business terms, that means keep going
as best we can while minimizing our exposure to risks. With
that thought in mind, and in the spirit of being helpful
neighbors, this issue of Verification Horizons
(http://lyris.mentor-info.com/t/10265...74/11813/3344/)
will show you how Mentor Graphics® can help you reduce
risk across your verification processes.

Our feature article
(http://lyris.mentor-info.com/t/10265...74/11814/3345/)
for this issue is by Mentor Graphics' Chief Verification
Scientist Harry Foster, introduces you to our new
Verification Academy series of online courses. The
Verification Academy provides the methodological bridge to
help you move from the high-level value propositions of
advanced verification to the nuts-and-bolts of how to
actually deploy these technologies. As we like to say, "The
Verification Academy is where education meets opportunity."
The courses are free, and it's just like having Harry stop
by for a visit! Well, maybe not quite, but it's a great
low-risk way of improving your organization's verification
processes. All courses are free and available online for
your convenience. Visit Verification Academy:
http://lyris.mentor-info.com/t/10265...74/11815/3346/

Our next article comes from our friends at Contemporary
Verification Consultants, a Questa Vanguard partner located
in India. In "Achieving a Higher Quality Design through
Questa," they show how constrained-random stimulus,
functional coverage, and the SystemVerilog DPI,
particularly as supported by Questa®, were used to more
efficiently create a more robust verification environment
than the previous directed-test environment. Read full
article:
http://lyris.mentor-info.com/t/10265...74/11816/3347/

Our next two articles deal with minimizing the risks
associated with verifying the increasing complexity of your
designs. In "Reduce the Risk of Expensive Post-Silicon
Debug,"
(http://lyris.mentor-info.com/t/10265...74/11817/3348/)
you'll see how the 0-In® CDC product can accurately
model the metastability inherent in your multi-clock
designs - you know, those intermittent bugs that usually
show up only in the lab. The article shows you how those
bugs can now be found and eliminated as part of your RTL
verification step.

Next we look at another type of synchronization in
"Mitigate Multi-Processor Synchronization Risks with
Processor Driven Verification."
(http://lyris.mentor-info.com/t/10265...74/11818/3349/)
This article discusses the requirements for an effective
multi-processor verification environment, especially in
synchronizing the processors with each other and providing
a powerful non-intrusive debug environment that shows each
processor and all of the hardware together.

Another area where many of our customers are looking to
reduce risk is when moving to the Open Verification
Methodology (OVM) from their current legacy Verification
Methodology Manual (VMM) environments. While they recognize
the advantages of the OVM, there are times when an
engineering team is reluctant to replace or rewrite legacy
VMM components, so interoperability has become a critical
issue. In December, Mentor Graphics released an open-source
interoperability library
(http://lyris.mentor-info.com/t/10265...74/11819/3350/)
to address this problem. "Reusing Legacy VMM VIP in OVM
Environments" gives an overview of this solution, which
addresses the requirements set out by the Accellera
Verification IP Technical Subcommittee. Read full article:
http://lyris.mentor-info.com/t/10265...74/11820/3351/

In our Partners' Corner, you'll find the third and last
installment of Doulos' "A Practical Guide to OVM"
(http://lyris.mentor-info.com/t/10265...74/11821/3352/)
series. This part of the guide shows how to get started
writing sequences in OVM 2.0.

We conclude this issue with our Consultants' Corner
article, on using the SystemVerilog "bind" construct to
provide a low-risk migration path to incorporate advanced
verification techniques in HDL-based testbenches. Read full
article:
http://lyris.mentor-info.com/t/10265...74/11822/3353/

So, in winter in New England, it's important to stay warm
and be thankful for friendly neighbors and family to help
in times of need. In a stormy economy, it's even more
important to protect yourself from the cold of risk in your
verification process. Remember that we here at Mentor
Graphics will be ready to help you weather the storm.

Respectfully submitted,

Tom Fitzpatrick
Verification Technologist
Mentor Graphics

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Download the full pdf version of this newsletter:
http://lyris.mentor-info.com/t/10265...74/11823/3354/
(PDF)

Submit a question or feedback on this issue at:
http://lyris.mentor-info.com/t/10265...74/11824/1359/

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