FPGA Central

Hello

We are pleased to share with you the latest Verification
news and information and hope you enjoy this month's
issue.

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IN THIS ISSUE:

> News
> Technical Papers
> Technical Events

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> News

* Intelligent Verification Offers Hope For "Smartening"
Up Verification

As seen on Chip Design's System Level Engineering
blog

http://chipdesignmag.com/sld/blog/20...-verification/

* Questa and The OVM Help SEAKR Dock a Verification
Environment for Space Age FPGAs

SEAKR pioneered the use of plastic encapsulated memory
(PEM) for storage systems for manned and unmanned space
applications, including the space shuttle and
international space station. Knowing that PEMs will
fail, their designs center around the ability to test
and correct errors associated with the effects of
space.

http://lyris.mentor-info.com/t/10688...74/12159/3445/
(PDF)

> Technical Papers

* Firmware Driven OVM Testbench
The Open Verification Methodology promotes a well
defined SystemVerilog transaction-level interface,
inviting integration of a host of verification
technologies. Firmware has proven effective for
functional verification of embedded hardware, so it
follows that OVM integration of a firmware execution
environment will advance the verification of embedded
systems. Read how Mentor's Seamless HW/SW co-simulation
tool has integrated with OVM.
http://lyris.mentor-info.com/t/10688...74/12160/3446/

* Tightening the Loop on Coverage Closure
Using a methodology such as graph-based intelligent
testbench automation to efficiently create verification
scenarios and stimuli is a powerful way to enhance
advanced verification environments to reduce common
verification headaches. Freeing up resources to focus
on the challenge of realizing a more ambitious
verification plan and of creating better functional
coverage metrics enables the verification team to
ensure that the device has been exercised in a far more
comprehensive manner. This paper explores a unique
solution to two challenges: definition of adequate
coverage measurement and the setup of efficient
automated testbenches.
http://lyris.mentor-info.com/t/10688...74/12161/3366/

* VPI for SystemVerilog Goes Dynamic
The SystemVerilog language supports a rich set of new
data types and the ability to create very general data
structures at runtime. VPI has historically had a
runtime information model whose data objects were
primarily static in nature. This paper examines a more
robust information model adopted in the 2009 LRM for
handling dynamic data. After reviewing the history of
VPI and the current conceptual programming model, we
will focus on class variables and objects and what
mechanisms there are to track dynamic object lifetime
and changes.
http://lyris.mentor-info.com/t/10688...74/12162/3447/

> Technical Events

* Intelligent Testbench Automation: Accelerating Coverage
Closure Online Seminar

This FREE web seminar provides a detailed technical
overview of the key features of the inFact intelligent
testbench automation solution. It covers:

- What graph-based verification is and how to generate
high quality tests while accelerating coverage
closure
- The benefits of eliminating redundant test sequences
to improve testbench effectiveness
- How intelligent testbench components fit into your
overall verification architecture
- What standards exist to help you get started with
verification

View at your convenience
http://lyris.mentor-info.com/t/10688...74/12163/3448/

* Verification Academy - Now Available!

First of its kind - unlike anything in the industry.

Provides you the materials and courses needed to
advance your verification skills to evolve your
organization's advanced functional verification
capabilities.

Current Course Modules:

- Assertion Based Verification
- Clock Domain Crossing

Visit us now
http://lyris.mentor-info.com/t/10688...74/12164/3346/

* Eliminating Clock-Domain Crossing Bugs with 0-In CDC
Web Seminar
June 2

This seminar teaches attendees about the types of
problems associated with clock domain crossings, the
things you can do to avoid these issues, and how to
apply an automated verification solution to ensure your
design is free of CDC issues.

More information and registration
http://lyris.mentor-info.com/t/10688...74/12168/3442/

* Finding the Toughest Bugs with 0-In Formal Verification
Web Seminar
June 4

This seminar explains how formal verification can most
effectively be used alongside simulation to allow
design and verification engineers to find more bugs,
earlier in the design process.

More information and registration
http://lyris.mentor-info.com/t/10688...74/12169/3443/

Have a friend or colleague that would like this
newsletter?
Feel free to pass it on!

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Tom Fitzpatrick
Verification Technologist

Mentor Graphics Corporation
http://lyris.mentor-info.com/t/10688...74/12167/1762/

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