FPGA Central

Hello

We are pleased to share with you the latest Verification
news and information and hope you enjoy this month's
issue.

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IN THIS ISSUE:

> News
> Technical Papers
> Product Information
> Technical Events

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> News

* Mentor Graphics inFact Tool Provides Plug-and-Play
Interoperability with OVM

The inFact intelligent testbench automation tool now
provides full support for the Open Verification
Methodology (OVM 2.0). The inFact tool uses systematic
algorithms, which allow it to rapidly produce unique,
non-redundant test cases. When broad test coverage is
important, the inFact tool's ability to move
linearly towards coverage closure can reduce test
repetition by 10x, providing more complete test, more
quickly.

http://lyris.mentor-info.com/t/10178...74/11715/3317/

> Technical Papers

* Methodology for Board Level Functional Simulation and
Hardware/Software Co-Verification Using Seamless
With less time to deliver these complex designs, the
importance of delivering a first-time correct design
and earlier hardware/software integration is becoming a
priority in the product design cycle. One way to
achieve the goal of a first-time correct hardware
design is to use board level functional simulation. The
Mentor Graphics Seamless® co-verification tool can
be used in the board level simulation environment to
perform hardware/software co-verification before the
first physical prototype boards arrive in the lab. This
not only provides earlier hardware/software integration
testing, but also provides earlier and greater
visibility of any problems that may arise during that
integration.
http://lyris.mentor-info.com/t/10178...74/11716/3318/

* Harvesting Real Productivity with Simulation Farms
This paper examines a graph-based technique for
describing and spatially distributing a verification
task efficiently across multiple machines in a
simulation farm. Design examples are used to explore
typical applications of this technique.
http://lyris.mentor-info.com/t/10178...74/11717/3319/

* The Value of Combining Processor-Driven Testbenches
with Traditional HDL Testbenches
This article discusses three distinct methods of
developing and executing processor-driven tests (PDT),
which are test vectors driven into the design via the
processor bus. For designs that incorporate or
interface to an embedded CPU, PDTs can be a valuable
addition to the functional verification test suite,
because they can detect design errors that may be
missed by more traditional HDL testbenches.
http://lyris.mentor-info.com/t/10178...74/11718/3320/

* A Scalable Approach for TLM across SystemC and
SystemVerilog
Many attempts have been made to mix SystemC and
SystemVerilog in advanced verification environments.
The paper addresses the limitations of these current
approaches, specifically in terms of scalability for
multiple transactions types and dynamic allocation of
data to be transferred across the language boundary. A
general and scalable method for mixing SystemC and
SystemVerilog data transactions and models will be
presented, accompanied by working example code taken
from real-life projects.
http://lyris.mentor-info.com/t/10178...74/11719/3321/

> Product Information

* Learn how to achieve more verification per cycle, not
just more cycles of verification

Have more to verify in your design than you have time
to achieve it? Would you like to realize a 10x gain in
overall verification productivity?

An intelligent testbench automation solution can
dramatically increase verification productivity while
radically decreasing test case volume. Mentor
Graphics' new inFact intelligent testbench
automation tool uses intelligent algorithms to
synthesize meaningful testbench sequences while
allowing the user to set verification goals prior to
simulation and determine verification priorities.

* Video 1

Learn how to use intelligent testbench automation to:

- Eliminate redundant tests
- Achieve more efficient functional coverage
- Make verification smarter

* Video 2

Hear about advanced features that improve ease of use
through the use of a sophisticated integrated
development environment (IDE).

* Video 3

See how inFact can deliver dramatic improvements in
time-to-coverage by replacing a constrained-random
stimulus generator.

View videos
http://lyris.mentor-info.com/t/10178...74/11720/3322/

* Ideal Platform for HW/SW Integration

Seamless enables users to debug hardware/software
integration issues early in the design cycle by running
embedded software on a simulation model of the embedded
hardware. Seamless delivers full debug control and
clear visibility of the interaction of hardware and
software in your processor-based embedded design.
Seamless provides an ideal platform for identifying
critical HW/SW integration issues prior to the
availability of an FPGA or silicon prototype.

View video
http://lyris.mentor-info.com/t/10178...74/11721/3323/

> Technical Events

* Improve Your Simulator Performance and Capacity with
the New Release of ModelSim Web Seminar
March 25 - 10:00am - 11:30 EDT

This technical discussion will highlight improved
simulator performance and capacity innovation, advanced
debug productivity and the best Mixed Language
platform. In addition, will cover new developments
including, regression test suite throughput, IEEE VHDL
and Verilog encryption language support, hyperlinked
source navigation and many other debug improvements.
This session will provide insight on how you can
leverage the many new ModelSim capabilities to help
maximize your verification efficiency today.

More information and registration
http://lyris.mentor-info.com/t/10178...74/11722/3300/

* Is My Low Power Design Switched-On? Web Seminar
April 7 - 12:00pm - 1:30pm CDT

The need for high return power management techniques
creatse new design and verification challenges across
the scope of a project. This goal of this seminar is to
give you a solid understanding of the concepts of power
management verification strategies, and how to best
utilize Questa Power Aware technology to verify the
functionality of your low power design.

More information and registration
http://lyris.mentor-info.com/t/10178...74/11723/3315/

* Clock-Domain Crossing Verification for FPGAs Web
Seminar
April 14 - 12:00pm - 1:30pm CDT

This seminar teaches attendees about the types of
problems associated with clock domain crossings, the
things you can do to avoid these issues, and how to
apply an automated verification solution to ensure your
FPGA is free of CDC issues. 0-In CDC supports the
leading FPGA vendors.

More information and registration
http://lyris.mentor-info.com/t/10178...74/11724/3324/

Have a friend or colleague that would like this
newsletter?
Feel free to pass it on!

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Tom Fitzpatrick
Verification Technologist

Mentor Graphics Corporation
http://lyris.mentor-info.com/t/10178...74/11726/1762/

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