FPGA Central

October 2009   

  Xilinx and ARM to Bring ARM IP into Xilinx FPGAs
Xilinx® and microprocessor IP vendor ARM announced they are collaborating to enable ARM processor and interconnect technology on Xilinx FPGAs. Xilinx is adopting ARM® Cortex processor IP, using performance-optimized ARM cell libraries and embedded memories for their future programmable platforms. In addition, ARM and Xilinx are working to define the next-generation ARM® AMBA® interconnect technology they will enhance and optimize for FPGA architectures. To learn more about the announcement visit…



  Xcell Journal Issue 69 Available Now
Xilinx Spartan-6 FPGAs Enable PCI Express Compliant System Design for Low-Power, Low-Cost Connectivity Applications
Xilinx Demonstrates New Broadcast Offerings That Lower Cost and Power of Serial Digital Interfaces
Xilinx Sales Up 10% Sequentially; Quarterly Dividend Increased $0.02 Per Share

Virtex FPGAs
Xcell Journal Cover Story: Xilinx FPGAs to Power Next-Generation Networked Battlefield
Xcell Journal issue 69’s cover story examines the US Defense Department’s Global Information Grid (GIG)-the elaborate worldwide network that it the uses to coordinate intelligence and military actions worldwide--and how the Defense Department and its many contractors are using Xilinx® FPGAs to speed up the GIG and thus the response times to threats. Read it!
Xcell Feature Story: Improving DDR SDRAM Efficiency with a Reordering Controller
In this article, Nokhu Systems’ engineer Leith Johnson describes how the Virtex®-6 memory controller achieves excellent sustained transfer rates for real-world workloads. Read it!
High Performance IBIS-AMI Simulation Models Released for Virtex-5 GTX/GTP SerDes Cores
Xilinx® has released IBIS-AMI SerDes simulation models that allow systems designers to analyze their serial channel designs before manufacture, accurately predicting performance and operating margin. Pre-layout analysis with IBIS-AMI models and SiSoft's Quantum Channel Designer software increases design quality by allowing designers to simultaneously co-optimize their channel design and equalization setup. SiSoft and Xilinx are presenting a complimentary webinar introducing the new models and how they can be used to accelerate your design cycle. You can also download the Virtex®-5 GTP and GTX IBIS-AMI models from here...
Xcell Feature Story: Splayed Design Makes Pin Fin Heat Sinks Cooler
In this tutorial article, Cool Innovation CTO Barry Dagan gives us an overview and some analysis of pin fin heat sinks to keep FPGAs cool. Read it!
Xcell Feature Story: Supercharge MicroBlaze Processing with Hardware Acceleration
In this feature story, Xilinx® FAE Karsten Trott describes how adding hardware acceleration to the MicroBlaze™ can dramatically speed up system performance. Read it!
Design Tools
Xcell Section: Overview of Recent Xilinx Tool & IP Updates
Xilinx® is continually improving its products, IP and design tools as it strives to help designers work more effectively. In this section of Xcell, we list the most current updates to the flagship FPGA development environment, the ISE® Design Suite, as well as to Xilinx IP, as of September 2009. Read it!
Xcell Section: Tools of Xcellence
In this issue of Xcell Journal, the Tools of Xcellence section features interview with the AvNu Alliance, which is trying to create a new standard to facilitate interoperability of various AV systems. The section also includes interviews with mixed-signal semiconductor and IP signal-compression vendor Samplify Systems on their latest version of their Prism compression technology. It also includes interviews with Opal Kelly about their new USB-in-an-FPGA module, with tool vendor Aldec about their new low-cost simulator, and last but not least with Innovative Integration about their new X5 G12 XMC I/O module family. Read it.
Additional Industry Standard Protocol Support in Xilinx GT Wizards
The LogiCORE™ IP Spartan®-6 GTP, Virtex®-6 GTX and GTH Transceiver Wizards automate the task of creating an HDL wrapper to configure the high-speed serial GT transceivers. Their respective menu-driven interfaces add more pre-defined templates for popular industry standards so you can create your own custom protocol starting from a pre-defined template or from scratch. The Spartan-6 GTP Transceiver Wizard support CPRI™, DisplayPort, Gigabit Ethernet, HD-SDI, OBSAI, PCI EXPRESS® (PCIe®) generation 1, Serial RapidIO, XAUI, Aurora 8B/10B and SATA-I. The Virtex-6 GTH Transceiver Wizard support 10-Gigabit Ethernet, 10G Base-R, and OTN OTU2. The Virtex-6 GTX Transceiver Wizards support Aurora (8B/10B and 64B/66B), CPRI™, Gigabit Ethernet, Interlaken, OBSAI, PCI EXPRESS ® (PCIe®) generation I and II, Serial RapidIO, XAUI and RXAUI. Visit the Architecture Wizards page to learn more.
ISE Design Suite 11.3 Update is Now Available
Version 11.3 of the ISE® Design Suite includes a host of improvements and new features. Keeping your installation up-to-date is the easiest way to ensure optimal design results. To update your existing ISE Design Suite installation to the latest version, visit the Xilinx® Product Update Site. New installations require the ISE Design Suite 11.1, available at the Xilinx Product Download and Licensing Site, before installing ISE Design Suite 11.3.
Start your Virtex-6 HXT FPGA Design Today with ISE Design Suite 11.3
This latest release of the ISE® Design Suite provides support for the new Virtex®-6 HXT FPGA, delivering the industry's highest bandwidth FPGA with up to 72 serial transceivers for high-bandwidth applications--such as bridging, switching, and aggregation--in wired telecommunications and data communications systems. Learn more and download a free 30-day evaluation of ISE Design Suite 11.3.
ISE Design Suite: DSP Edition 11.3 Extends Designer Productivity
ISE® Design Suite: DSP Edition 11.3 includes extended device support for the Virtex®-6 HXT, Virtex-6 speed grade -1L (Low Power), and Virtex-5Q FPGA families. It also includes new OS support for Microsoft Windows Vista and 64-bit Red Hat and SUSE Enterprise Linux. It also has JTAG hardware co-simulation for the Spartan®-6 FPGA SP605 Development Platform, System Generator for DSP blockset enhancements and enhancements to DSP LogiCORE™ IP. Learn more and download a free 30-day evaluation of the ISE Design Suite: DSP Edition.
ISE Design Suite: Embedded Edition Extends Support for Virtex-6 and Spartan-6 FPGA Families
In addition to improvements in the logic design tools in all ISE® Design Suite Editions, the ISE Design Suite: Embedded Edition includes several enhancements. Among them, it now supports Platform Flash XL for command line users and contract-based IP licensing. XPS in the tool suite now supports Clock Generator for both the Virtex®-6 and Spartan®-6 FPGA families. The suite also extends Clock Wizard support for the Multi-port Memory Controller (MPMC) in both the Virtex-6 and Spartan-6 FPGA families. Learn more and download a free 30-day evaluation of the ISE Design Suite: Embedded Edition.
New White Paper: Capabilities to Maximize Productivity for FPGA Debug and Verification
Whether your task is to verify the functional correctness of a design, ensure adequate timing performance, or to quickly bring up a hardware platform in the lab environment, efficient verification and debug typically requires evaluating the design from multiple perspectives. To effectively complete these tasks, you need a complete and well integrated set of capabilities. Learn more in this technical paper about the spectrum of verification and debug tools that the ISE Design Suite puts at your disposal. Visit...
New Whitepaper: Accurately Analyzing Power in a Simulink Software Model-Based Design Flow
A large part of an effective power strategy is accurate analysis. This new whitepaper describes how the Xilinx Power Estimator (XPE) can perform a power analysis at any time during the DSP design cycle. At each stage of the design, the Xilinx Power Analyzer (XPA) can provide a post-mapping and post place and route power analysis. Lastly, the Xilinx power-driven implementation can optimize for power by using different power optimization techniques in conjunction with other optimization algorithms. Learn more in this new whitepaper.
Boards & Kits
Accelerate Your Designs Right Out of the Box with the Spartan®-6 FPGA SP605 Evaluation Kit
The Spartan®-6 FPGA SP605 Evaluation Kit is an ideal entry-level development environment for evaluating the Spartan-6 family and is ideal for power-sensitive applications that require transceivers. Use this board if you are developing consumer, infotainment, video, and other cost- and power-sensitive applications. The new kit is part of the Base Targeted Design Platform, which provides an integration of hardware, software, IP, and pre-verified reference designs so you can begin development right out of the box. Get yours today!
Audio, Video & Broadcast
Visit Xilinx at InterBEE 2009-Booth #6115/Hall 6, November 18-20, Makuhari Messe
Join the Xilinx® Broadcast team at InterBEE 2009 for real-world demonstrations of the latest developments in programmable solutions for the broadcast market. Learn more about the show now here...
Consumer
Visit Xilinx at CES 2010-South Hall 4/ 35126MP, January 7-10, Las Vegas Convention Center
Join the Xilinx® Consumer team at CES 2010 for an exhibition of leading-edge, high-volume, cost-sensitive solutions for video applications. Learn how to register as a Xilinx guest and receive a FREE Exhibits Plus pass to the show now.
Xcell Feature Story: How to Tame the Power Beast in Consumer Handheld MPUs
In this feature story, design services firm eInfoChips describes their increased use of FPGAs over ASICs for handheld device development and how they deal with power issues. Read it.
Industrial/Scientific/Medical
Xcell Feature Story: FPGAs Help Measure Trajectory of Particles in CERN's Proton Synchrotron
In this feature story, engineers at Beam Ltd. describe how they teamed with Alpha Data to create an elaborate FPGA-heavy system to track in real-time particles moving near the speed of light in CERN’s Proton Synchrotron. Read it!
Xcell Feature Story: Hardware-Centric Approach Builds More Reliable Medical Devices
In this feature, HEI describes their hardware-design-centric method and tool use for medical device designs. Read it!
Wireless Communications
Visit Xilinx at SDR'09-Booth #19, December 1-4, Hyatt Regency Crystal City
Join the Xilinx® Wireless team at SDR’09 for the latest programmable platforms for software-defined radio in military, civil, and commercial applications. Don’t miss out on our schedule of workshops, tutorials, and technical sessions. Learn more about Xilinx participation at the show and register for the show now.
Xcell Feature Story: Implementing Wireless LAN Interface in an FPGA
In this article, engineers at Wipro-NewLogic describe how they use Xilinx FPGAs to build a development board to prove out WLAN IP develop. The article describes how their engineers were able to program the FPGA to run WLAN IP at full speed and even passWi-Fi certification. Read it!
Services, Events & Education
OnDemand Video--Xilinx Featured at EE Times Virtual Conference
This virtual conference explores the challenges faced by developers of ASIC- and FPGA-based SoCs, including an in-depth look at the state of chip design economics, the quest for plug-and-play intellectual property, the state of the verification bottleneck, and the need for better integration between analog and digital design flows. Register & View Today
New Webcast on November 17th: “Accelerate FPGA Designer Productivity with ISE Design Suite”
Register to view the upcoming Tue Nov 17th web seminar “Accelerate FPGA Designer Productivity with ISE Design Suite” to learn tricks and tips on how to effectively and efficiently design new systems based on the popular Spartan®-6 and Virtex®-6 FPGAs. Visit...
Updated Course: DSP Design Using System Generator
The Xilinx® Global Training Solutions group has updated the popular course DSP Design Using System Generator in support of the release of Virtex®-6 and Spartan®-6, and the ISE® Design Suite version 11.3. To learn more, visit...
Updated Course: ISE Design Tool Flow
The Xilinx® Global Training Solutions group has updated the popular ISE Design Tool Flow customer training course in support of the launch of the Virtex®-6 & Spartan®-6 FPGA families as well as ISE® Design Suite version 11.3. To learn more, visit...
Updated Course: Essentials of FPGA Design
In support of the release of the Virtex®-6 and Spartan®-6 FPGA families and ISE® Design Suite version 11.3, The Xilinx® Global Training Solutions has updated the popular course ISE Design Tool Flow. For more information, visit...
Updated Course: Designing for Performance
The Xilinx® Global Training Solutions group has updated the popular customer education course Designing for Performance in support of the release of the Xilinx® Spartan®-6 and Virtex®-6 FPGA families and the ISE® Design Suite. For more information, visit...
Updated Course: Designing with Multi-Gigabit Serial I/O
The Xilinx® Global Training Solutions group has updated the popular customer education course Designing with Multi-Gigabit Serial I/O in support of the release of the Xilinx® Spartan®-6 and Virtex®-6 FPGA families and the ISE® Design Suite. To learn more, visit...
Updated Course: Debugging Techniques Using the ChipScope Pro Tools
This updated course from the Xilinx® Global Training Solutions group extends this previous 1-day class to 2 days with a focus on the basics and practical applications of the ChipScope Pro Tool for ISE® Design Suite 11.3 and Xilinx’s new FPGAs. For more information, visit...
Free Xilinx E-Learning Sessions Updated for New FPGAs and Tools
The Xilinx® Global Training Solutions group has updated several of its free e-learning sessions to reflect the nuances of the new Virtex®-6, Spartan®-6 and the ISE® Design Suite version 11. Updated sessions include Basic FPGA Configuration (Parts 1 & 2); Architecture Wizard and PinAhead; Basic FPGA Architecture: Slice and I/O Resources (for Spartan-6 & Virtex-6 FPGAs); ChipScope Pro Software; Virtex-6 and Spartan-6 FPGA HDL Coding Techniques (Parts 1 & 2); Power Estimation; Synthesis Options; Basic HDL Coding Techniques (Part 1 & 2). To take these updated courses, visit...
Xilinx Partner Spotlight
Curtiss-Wright FMC-520 DAC FPGA Mezzanine
Curtiss-Wright Controls Embedded Computing has introduced the FMC-520 DAC FPGA mezzanine card for DSP applications. The card is based on the VITA 57 standard and integrates 2- (1 GSPS) or 4-channels (500 MSPS) of analog output into embedded computing systems, dependant on the output conversion rate selected. Visit...
High Level Synthesis From MatLab Language
Synopsys' new Synphony HLS is a language & model-based synthesis product that provides an efficient path from algorithm to silicon. Designers construct high level algorithm models from the MATLAB® language & IP model libraries, and then quickly synthesize optimized RTL implementations for Xilinx® FPGAs. Visit...
Reserve a Spot at the Cadence Virtual Conference
Insure your spot at the Cadence Allegro and OrCAD 16.3 Virtual Conference scheduled December 2nd. Get a first look at the latest technology in PCB and IC Packaging and also view our spotlight on our key strategic partners including of course Xilinx® who will be participating in our FPGA Design booth. Visit...
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