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IC Journal Update




a techfocus media publication :: May 19, 2009 :: volume VI, no. 07









FROM THE EDITOR



You might think that floorplanning, placing, and routing a complex IC is a non-trivial task. And you'd be right. So... now take that and add the possibility that the die you're creating might be stacked with other dice in a package, and now your floorplan has to take that into account as well. A non-trivial task now made even less trivial. This week we take a look at work that Javelin has done, along with IMEC, to help manage the process of designing dice for through-silicon via (TSV) applications.

Thanks for reading! We love to get your feedback and suggestions; please send either or both to:
comments (AT) ICJournal (DOT) com. You can also make yourself heard publicly by going to our Journal Forums.

Bryon Moyer - Editor
IC Design and Verification Journal









EVENTS & ANNOUNCEMENTS











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LATEST NEWS



May 19, 2009



ARM Selects Jasper for Formal Verification of IP



Development tools for NXP’s Cortex-M3™ based LPC176x series



Continuous Computing and picoChip Announce Ground-Breaking Agreement to Create LTE Hardware-Software Reference Design



Tower and Jazz Semiconductor Announce Industry’s First Scalable Rdson Design Tool for Growing Power Management Market



New Sopheon Software Links Idea Development to Strategic Product Planning and Execution



Spring Release of Sourcery G++™ Offers Improved Performance and Ease-of-Use



May 18, 2009



Real Intent Announces New Releases of Ascent and Meridian



The SPIRIT Consortium Releases SystemRDL 1.0



SpringSoft Introduces Structured Method for SystemVerilog Testbench Debug and Analysis



Agilent Technologies’ EMPro 2009 Improves Integration with Advanced Design System



May 15, 2009



OMG and INCOSE Join Resources on OMG’s New Certification Program for Systems Modeling Language Practitioners



May 14, 2009



Agilent Technologies Introduces Accessories that Extend Dynamic Range of Award-Winning InfiniiMax Active Probes



Synopsys PrimeTime PX Power Analysis Solution Achieves Broad Market Adoption



Silicon Frontline Technology, Founded by EDA Technologists, Announces Post-Layout EDA Verification Software



May 13, 2009



Tower and Jazz Semiconductor Announce Call for Papers for 2009 Analog-Intensive Mixed-Signal Circuits, Applications, and Technology (AIMS-CAT) Conference



Novell Uses dynaTrace To Build High-Performance Software Faster









CURRENT FEATURE ARTICLES



Managing More Freedom
Finding the Right Path for a 3-D Chip
(Bryon Moyer)
IP Mates, IP Stars and IP Trolls
(Dick Selwood)
Library Science
Magma’s SiliconSmart, Now With Functional Recognition (Bryon Moyer)
More Than A Zen Thing
A Look at Functional Qualification
(Bryon Moyer)
Does Noise Analysis Accuracy Really Matter?
by Michael Jacobs and Trisha Kristof, Cadence Design Systems
Bringing It Together – Some of It, Anyway
Synopsys Announces Lynx and Discovery
(Bryon Moyer)



JOURNAL WEBCASTS



NEW! CHALK TALK Improving Software Development Productivity With Virtual Platforms. Are your SoC and embedded design projects increasingly dominated by software development schedules? Join Amelia Dalton as she talks with Frank Schirrmeister of Synopsys about ways to improve software development productivity using virtual platforms. (Synopsys)

CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK Catapult C Synthesis Designing a JPEG Compression Engine. Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics)



[click here for more webcasts]












Managing More Freedom
Finding the Right Path for a 3-D Chip
(Bryon Moyer)

It’s all about degrees of freedom. The more of them you have, the more options you have. In the mechanical world, we think of it primarily as the number of dimensions within which you can move: a universal joint can bend in any direction because it has three axes of rotation, one for each of the three spatial dimensions. Three degrees of freedom. When an ant walks on a beach ball, even though it’s a 3-D object, it has only two degrees of freedom because it’s constrained to the surface of the ball. When routing signals on an IC, each layer provides additional degrees of freedom in two dimensions, with vias providing a third dimension that gets you from layer to layer.

Having more options can be good, but it also adds complexity. As any parent will know, just try giving a young boy full choice of what to wear to school: you’ll never get a decision. Restrict the decision to one of two shirts, and he can pick one and be on his way. Even scarier is the lockup that can occur if you offer a committee too many choices. Heck, give me a list of the dozens of possible cell phones and calling plans from which to choose, and I’m likely to end up quivering in a primordial cave, wishing the modern world would just go away and leave me alone.

So the benefits of choice are tempered by the stress of making life more complicated. From an IC perspective, adding degrees of freedom by using vias to interconnect metal layers on a chip is, of course, old news, and its complexities can be managed with well-established tools. It’s been taken a step further in the attempt to stack dice on top of each other using through-silicon via (TSV) technology. This provides an electrically clean, dense way of connecting signals from one chip to another by etching a hole through the silicon and filling it with metal. The earliest uses of this have simply stacked identical dice on top of each other for such purposes as increasing the amount of memory within a single package. [more]






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