FPGA Central

IC Journal Update




a techfocus media publication :: April 21, 2009 :: volume VI, no. 03









FROM THE EDITOR

Dozens of different tools. Long, complicated scripts that need dedicated engineering support. Some stuff over here for digital, some other stuff over there for analog, something yet different to bring them together (along with some reverently-mumbled incantations to make sure it all works). There’s no such thing as a flow along the long path required to take an idea to a complete mask set for an IC. Synopsys has made a couple recent announcements that try to help corral some of this chaos a bit more; this week we take a look at their Lynx and Discovery platforms.

Thanks for reading! We love to get your feedback and suggestions; please send either or both to:
comments (AT) ICJournal (DOT) com. You can also make yourself heard publicly by going to our Journal Forums.

Bryon Moyer - Editor
IC Design and Verification Journal









EVENTS & ANNOUNCEMENTS











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LATEST NEWS



April 21, 2009



Tesla Motors Uses MathWorks Tools for Model-Based Design to Develop World’s First Electric Production Sports Car



Apache Design Solutions Introduces Totem, the Industry’s First Power and Noise Integrity Platform for Analog and Mixed-Signal Designs



JasperGold Adds Proof Accelerators For Fast, Thorough Verification Speeds end-to-end proofs for data packet integrity, RAM, and multipliers



DoD Advanced Architect Edition respond directly to the architectural framework needs of the US DoD, its suppliers and DoDAF users



April 20, 2009



Mentor Graphics Strengthens Its Automotive Solutions with New Integrated AUTOSAR Design Environment



ARM Announces Availability of Industry’s Broadest 40nm G Physical IP Platform



Altera Delivers Stratix IV GX Transceiver Signal Integrity Development Kit



Agilent Technologies Introduces Latest In-Circuit Tester with Digital Capabilities, Low-Cost Fixturing



April 17, 2009



Jasper Patent Speeds Debug During Verification



April 16, 2009



Pigeon Point Systems Ships ATCA Starter Kits Based On Actel Fusion Mixed-Signal FPGA



April 15, 2009



Coverity® Introduces Software Build Analysis



PICMG Consortium Releases New COM Express Design Guide



Agilent Technologies, Symwave Collaboration Enables First-in-Class, High-Quality USB 3.0 Devices



Apache Design Solutions to Host Noise Integrity Workshop at the Design Automation and Test, Europe (DATE) Conference





CURRENT FEATURE ARTICLES

Bringing It Together – Some of It, Anyway
Synopsys Announces Lynx and Discovery
(Bryon Moyer)
But What Does It Mean?
Tagging, Indexing, and Querying Behaviors in RTL Designs (Bryon Moyer)
Finding Waldo
A Look at Silicon Debug – After You’ve Got Silicon
(Bryon Moyer)
Quantum of Solids
A Look at the Rapidly Evolving State of MRRG
(Bryon Moyer)
Using Power and Integrity in the Same Sentence
Apache Provides Hierarchical Dynamic Power Integrity Analysis(Bryon Moyer)
Reducing Test Time and Cost  for an Advanced Wireless Device by Alessio Pricco (STMicroelectronics), Jay Jahangiri (Mentor Graphics), and Kan Thapar (Mentor Graphics)

JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK Catapult C Synthesis Designing a JPEG Compression Engine. Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics).



CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)



[click here for more webcasts]












Bringing It Together – Some of It, Anyway
Synopsys Announces Lynx and Discovery (Bryon Moyer)





The EDA world is rife with point solutions. No sooner might you think it’s time to stitch together a unified flow when some new requirement of some new technology makes some new point tool necessary for effective design.

And so it goes; an IC design environment might have a dozen or two (or more) tools that must be invoked at one time or another. It’s not a flow, it’s more like an artist’s palette, with all the capabilities laid out in a more or less unstructured fashion, and you dip your brush in one or the other as needed, ad hoc, to accomplish the design goals of a given project.

Synopsys and ARM have addressed this to some extent by their Manuals. There’s a Methodology one for low power. There’s a Methodology one for verification. There are the Reference Methodologies (RMs) for aspects of IC design. And some of these have been jointly published as non-trivial books. The idea is to capture best practices and document them to provide something more of a roadmap of the landscape and help engineers navigate.

Which is fine. But to me, when a methodology manual is required, it means the process being described isn’t clear, isn’t intuitive, isn’t obvious. If it really takes a map to get from here to there, then that means that the turns along the way won’t be clear, the signage will be poor, and it’s easy to get caught in suburban cul-de-sac traps that offer no easy escapes. [more]










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