FPGA Central

IC Journal Update




a techfocus media publication :: March 24, 2009 :: volume V, no. 12









FROM THE EDITOR



Noisy signals have become more and more of an issue as signal speeds have increased and “digital” signals have ended up looking more and more analog; this has driven the importance of signal integrity verification. Meanwhile, power has, of course, risen to the level of primary consideration. Combine the two and you have power integrity: the consideration of noise in the power grid. And you have our focus for this week’s feature article.



In addition, Mentor has contributed an article describing their experience implementing BIST in a project with ST Microelectronics. If you’re new to some of the issues of IC test, particularly test compression, you might find some help in our test compression review from last year.

Thanks for reading! We love to get your feedback and suggestions; please send either or both to:
comments (AT) ICJournal (DOT) com. You can also make yourself heard publicly by going to our Journal Forums.

Bryon Moyer - Editor
IC Design and Verification Journal









EVENTS & ANNOUNCEMENTS












Mentor Graphics inFact testbench automation solution is the first to use intelligent algorithms to synthesize meaningful testbench sequences while allowing the user to set verification goals prior to simulation and determine verification priorities. inFact workshops now scheduled for San Jose and Austin. More locations soon to be added.
Email infact_info (AT) mentor (DOT) com to save a spot.
Learn more now.




















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LATEST NEWS



March 24, 2009



Agilent Technologies Introduces Manufacturing 10G DCA with PON Filter Rates and Industry-First Smart Post Processing



Agilent Technologies Introduces Photonic Application Software for Next-Generation-Network Component Test



Vitesse Announces Signal Conditioner for 10G High-Density SFP+ Line Cards



Agilent Technologies Introduces Industry-First Waveform Analysis Solutions for Next-Generation Storage, Telecommunications Components and Systems



Summit Microelectronics Selects Berkeley Design Automation AFS Nano™



Agilent Technologies to Demonstrate Industry-First Optical Test Solutions for High-Speed Networks at OFC/NFOEC 2009



March 23, 2009



Sierra™ M6-2 Protocol Verification Platform Provides Advanced 6G SAS and SATA Analysis, Error Injection and Emulation



Sarnoff Europe Announces Silicon Proven ESD Cells for UMC 65nm, 0.13um CMOS and 0.18um HV CMOS Under New Low-cost Business Model



March 20, 2009



Robotics Trends Announces Stimulus Pricing For Robobusiness Conference & Exposition 2009



Agilent Technologies' Test Portfolio Now Includes Industry-First Automated USB SuperSpeed Pattern Generator Calibration



IEEE Approves New Low-Power Design Standard for Integrated Circuits In Electronic Systems



March 19, 2009



IR’s IR3725 Input Power Monitor IC with Digital Interface Delivers Superior System Accuracy for Energy-Efficient DC-DC Converters



Interface Development Suite supports creation of ultimate user experience for display-based designs



Agilent Technologies to Collaborate with ASTER for Seamless Test Coverage Analysis Across Test Platforms



Tanner EDA Announces 64-Bit Windows Version of Affordable, Interoperable and Easy-to-Use Analog/Mixed-Signal and MEMS Electronic Design Software; Version 14 Allows for Larger Designs, Runs up to 25% Faster



GCT Semiconductor Leverages MIPS Technologies' Analog IP for Mobile WiMAX™



March 18, 2009



MIPS Technologies Achieves Technical Milestones for USB 2.0 High-Speed PHY IP





CURRENT FEATURE ARTICLES



Using Power and Integrity in the Same Sentence
Apache Provides Hierarchical Dynamic Power Integrity Analysis (Bryon Moyer)
Reducing Test Time and Cost  for an Advanced Wireless Device by Alessio Pricco (STMicroelectronics), Jay Jahangiri (Mentor Graphics), and Kan Thapar (Mentor Graphics)
Showing Your True Corners
Solido Helps Analog Designers Cope with Process Variation (Bryon Moyer)
Emulate This!
Stirrings in the Hardware-accelerated Verification World (Bryon Moyer)
Braving the Black-and-White
ISSCC Highlights (Bryon Moyer)
Acquiring More Addicts
Easing into Formal Verification (Bryon Moyer)



JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK Catapult C Synthesis Designing a JPEG Compression Engine. Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics).



CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)



[click here for more webcasts]












Using Power and Integrity in the Same Sentence
Apache Provides Hierarchical Dynamic Power Integrity Analysis (Bryon Moyer)

Power is seductive. It has attracted the attention of universities, designers, tool vendors, journalists, and anyone who wants to be anyone in the silicon and systems worlds. Of course, unlike the situation in so many hallowed halls around the world, the aim here is to reduce power, not increase it (or gather it for oneself). Out of the limelight, however, is the stability of the power infrastructure: how robust is a chip’s power grid in the face of potentially wild gyrations of power draw as a chip is put through its paces? This is the realm of power integrity (two words that, in too many other contexts, have no place near each other), and, like signal integrity with respect to signal speed, it is all too often relegated to second-order status as compared to power.

There are a number of reasons why power integrity considerations are more important today than they once were. Back when chips were simpler conglomerations of data path and logic, there were obvious sources of noise that could be addressed in an ad hoc fashion. Heck, before that, transitions were slow enough that noise wasn’t even as much of an issue, period. Now there are numerous potential sources, and just blindly trying to fix things that might be a problem may not fix anything and will likely result in over-design. [more]








Reducing Test Time and Cost  for an Advanced Wireless Device 
by Alessio Pricco (STMicroelectronics), Jay Jahangiri (Mentor Graphics), and Kan Thapar (Mentor Graphics)

Designing wireless infrastructure chips at 65 nm and below introduced subtle failure mechanisms previously unobserved at larger process nodes. These new failure mechanisms, along with the requirements for better self-test in the field and limitations on available IC pins to interface with automated testing equipment, have resulted in tougher test requirements at STMicroelectronics.

STMicroelectronics’ advanced designs must be of the highest quality for demanding end-product applications. We use in-system test to ensure the device is functioning properly without having to remove it from a board or system. [more]











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