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IC Journal Update




a techfocus media publication :: March 17, 2009 :: volume V, no. 11









FROM THE EDITOR



We’ve seen before how the digital world dominates a lot of what happens in IC design. But many of the convenient conventions that apply to digital may not apply to analog, and any tools that are based on those conventions may not be applicable to analog. This week we look at an approach Solido is taking to help analog designers optimize their circuits on processes that have increasing levels of variation.

Thanks for reading! We love to get your feedback and suggestions; please send either or both to:
comments (AT) ICJournal (DOT) com. You can also make yourself heard publicly by going to our Journal Forums.

Bryon Moyer - Editor
IC Design and Verification Journal









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LATEST NEWS



March 17, 2009



Mentor Graphics Provides Complete 3D Variability Solution Addressing Density and Thickness Challenge



Denali IP Product Deployed in Celeno's Latest HD Video Wi-Fi Chip



Gemini Begins Shipment of GSim™, Industry’s Fastest SPICE-Accurate Analog Simulator



IPextreme Levels the Playing Field With Constellations™ Program



KlingStubbins Incorporates IES’ Integrated Analysis Tools Into Sustainable Design Process



Custom Silicon Solutions Announces the Availability of CSS68HC68W1



March 16, 2009



PolyCore Software Announces Multicore Communications Topology Mapping Tool



Synopsys Announces Yield Explorer - Design-Centric Yield Management for Product Engineering Teams



K-micro Announces Availability of FPGA Board for the CatsEye Development Systems



Atmel Introduces an AVR32 Digital Audio Gateway Reference Design for Digital Audio Streaming, Decoding and Playback



ON Semiconductor to Offer New Intellectual Property Blocks for Industry-Standard Interfaces, Microcontrollers and Peripherals



Synopsys Introduces Lynx Design System



Cadence Enhances Low-Power Solution Enabling More Predictable Power-Efficient Design



March 13, 2009



Solido Design CTO to Present Advanced Statistical Analog/Mixed-Signal Design Techniques Paper at ISQED



March 12, 2009



Virtutech and Partners Show Simics Full Systems Simulation at Multicore Expo



Fully integrated current-limited load switch simplifies hot swap management



March 11, 2009



EMA Announces Component Information Portal Version 2.2 Including an Expanded Foundation Library



Patent and Licensing Experts to Reveal Best Practices for Protecting, Managing and Leveraging Intellectual Property at 2009 IP Symposium



10th Annual ISQED Draws Record Attendance; Free Registrations Include Access to Exhibits, Technical Presentations, Keynotes and Embedded Tutorials



TATA Autocomp Systems Ltd. Expands its Deployment of Mentor Graphics Electrical Systems Design Tools



DO-254 Users Group Forms a US Chapter, Affiliates with European Counterpart



Carbon Announces Availability of ARM Cortex Models



Apache and NXP Collaborate to Address 45nm Power Integrity Challenges for Advanced Digital Processor Design



ViXS Systems Selects Virage Logic’s High-Performance Intelli™ DDR 2/3 Memory Interface IP Solution for Video Processing Systems





CURRENT FEATURE ARTICLES



Showing Your True Corners
Solido Helps Analog Designers Cope with Process Variation (Bryon Moyer)
Emulate This!
Stirrings in the Hardware-accelerated Verification World (Bryon Moyer)
Braving the Black-and-White
ISSCC Highlights (Bryon Moyer)
Acquiring More Addicts
Easing into Formal Verification (Bryon Moyer)
Evaluating a Design Data Management System
by Scott Woods, Integrated Device Technology, Inc.
Standardising on Analogue
(Dick Selwood)
Maximizing Flash Lifetimes
A Look at Flash Management Strategies
(Bryon Moyer)
The Road Ahead
The ITRS Updates The Forecast (Bryon Moyer)



JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK Catapult C Synthesis Designing a JPEG Compression Engine. Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics).



CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)



[click here for more webcasts]












Showing Your True Corners
Solido Helps Analog Designers Cope with Process Variation (Bryon Moyer)

A lot has been written about the increasing difficulty of optimizing a design as process dimensions have become increasingly minute. Not only is it harder to balance performance against area, but power must be considered as well. Managing yield is a constant struggle since it’s no longer a question of where to cut off a distribution tail: it’s a question of how to fix the distribution so that you don’t over- or under-design your product. Too sloppy and you lose a lot of yield; too rigid and you will chew up too much silicon.

As difficult as this is, most of the attention has been focused on digital. It’s even harder for the poor analog folks, for whom “performance” may have diverse meanings according to the intent of the circuit. In the digital world, performance means “speed.” But performance in an analog circuit might include things like gain or phase margin or signal-to-noise ratio (SNR) or bizarre-sounding beasts like “spurious-free dynamic range” (SFDR). Easy for them to say…

Part of figuring out your distribution is figuring out the extent of performance: how bad or good can it get? There is a particular combination of process points that will give you worst-case and best-case performance points. In the digital world, where speed rules, this is evaluated by applying combinations of variations that cause your transistors (N-channel and P-channel) to be either fast or slow. There are two transistor types, giving you two variables, meaning you get four combinations, typically denoted as FF (Fast-Fast), FS (Fast-Slow), SF, and SS. These are the process corners. Somewhere in between is the “nominal” or “typical” point.

You can think of these points as defining the corners of the sandbox within which you will play. Instead of having to sweep across a wide range of process settings, you can just work at the corners to figure out where the worst case is; this speeds up simulation tremendously since you’ve reduced a “very-very-very-many point” problem to a 4- or 5-point problem. However, the process settings that define the corners for digital performance may not necessarily be the same as those defining the corners for various analog performance metrics. Just because both N-channel and P-channel transistors are as fast as possible doesn’t necessarily mean that’s the point of best SNR for a circuit; there may be a completely different process point that acts as a corner for SNR. [more]












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