FPGA Central

IC Journal Update




a techfocus media publication :: March 10, 2009 :: volume V, no. 10









FROM THE EDITOR



We spend more time verifying than anything else. Trust but verify. So much verification. So little trust. It’s a sad world. But the amount of time we need for some of that verification can be reduced by actually casting our design ideas into hardware instead of only using software to simulate. This week we take a look at the emulation world, and, in particular, a couple of recent emulation announcements. (Although we might get stuck on terminology.)

Thanks for reading! We love to get your feedback and suggestions; please send either or both to:
comments (AT) ICJournal (DOT) com. You can also make yourself heard publicly by going to our Journal Forums.

Bryon Moyer - Editor
IC Design and Verification Journal









EVENTS & ANNOUNCEMENTS












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LATEST NEWS



March 10, 2009



ACM Turing Award Goes to Creator of Influential Innovations in Computer Software Design



Synopsys DesignWare USB 2.0 nanoPHY and PCI Express 1.1 PHY IP First to Achieve Compliance in UMC's 65-Nanometer Process Technologies



Agilent Technologies to Unveil Industry-First Optical Modulation Analyzer for 40/100G Physical Layer Test at OFC/NFOEC 2009



CebaTech Launches CebaRIP Library of Rapidly Tunable Intellectual Property Cores



March 9, 2009



Tundra Semiconductor Selects Synopsys as Its Primary EDA Partner



Actel’s New Fusion Embedded Development Kit Showcases Unique Mixed-Signal FPGA Design Capabilities



Mentor Graphics Precision Synthesis Tool Family Supports Altera’s Stratix IV GT and Arria II GX FPGA Devices



Agilent Technologies Announces GC Productivity, Performance Boosts, Next-Generation HPLC-Chip/MS, and Collaboration with EPA at Pittcon 2009



IAR Systems: Fast Debugging with Plug-and-Play J-Trace for ARM® Cortex™-M3 and IAR Embedded Workbench



K-micro Announces Availability of CatsEye Development Systems



March 6, 2009



Geensys announces Reqtify 2009-1a



EDA Tech Forum Worldwide Event Series Begins March 26, 2009



Geensys facilitates the validation and verification of AUTOSAR systems with launch of ASIM for AUTOSAR Builder



March 5, 2009



Synopsys DesignWare IP for PCI Express First IP to Pass Agilent Technologies' Inline Error Injection Testing



Mentor Graphics Eldo Simulator used by STMicroelectronics to Characterize 32nm Cell Libraries



Artisan announces Artisan Workbench



Alvand Technologies’ Ultra-Low Power ADC/DAC IP Has Been Selected By Faraday Technology for High-Performance, and Next-Generation Mixed-Signal ASICs



March 4, 2009



GSA and MOS-AK Merge Efforts to Form the GSA Modeling Working Group



Agilent Technologies Introduces Industry-First, Most Comprehensive DDR3 Test Suite with Industry's Fastest Full Channel Logic Analysis Tool



Compact RTOS Evaluation platform simplifies RTOS and stack selection and testing



Agilent Technologies' New System-Level Communications Design Software Speeds Development Cycle





CURRENT FEATURE ARTICLES



Emulate This!
Stirrings in the Hardware-accelerated Verification World (Bryon Moyer)
Braving the Black-and-White
ISSCC Highlights (Bryon Moyer)
Acquiring More Addicts
Easing into Formal Verification (Bryon Moyer)
Evaluating a Design Data Management System
by Scott Woods, Integrated Device Technology, Inc.
Standardising on Analogue
(Dick Selwood)
Maximizing Flash Lifetimes
A Look at Flash Management Strategies
(Bryon Moyer)
The Road Ahead
The ITRS Updates The Forecast (Bryon Moyer)
Open, Virtual and a Platform
(Dick Selwood)



JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK Catapult C Synthesis Designing a JPEG Compression Engine. Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics).



CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)



[click here for more webcasts]












Emulate This!
Stirrings in the Hardware-accelerated Verification World (Bryon Moyer)

When each chip you design is going to cost you millions in mask charges and other associated fees, and when any mistake in such a chip can cost you millions more, it makes sense that you’re willing to fork out some cash to help reduce the chances of a flub. And when getting to market sooner means dollars in your pocket, it’s likely that getting a chance to test your software earlier will also be worth some coin.

Of course, this is the whole reason anyone pays for good chip design tools (as opposed to simple software design, where a mistake – in theory – costs nothing but a follow-up patch). And it’s why a ton of that payment is for verification. And a non-trivial part of such verification can be allocated to hardware acceleration. Such acceleration not only gets you through more testing more quickly, but it also lets you emulate the system in which software will run quickly enough to where you can actually test out some of your software in advance of the hardware being available.

You wouldn’t necessarily think that the name for such an accelerator would be controversial, but, in a world where positioning is key, names are very important. We’re going to be stubborn here and call such accelerators emulators, even though that might cause some unhappiness in some quarters. It’s nothing personal or malicious, to be sure. But I’m getting ahead of myself.

There have been a couple of announcements in the somewhat staid-seeming emulation world lately. So it’s a good time to take a look around and put some context behind them. Frankly, there don’t seem to be that many emulator guys anymore. Some got bought, some disappeared. With what remains, there appear to be two broad classes of box: FPGA-based and custom-chip-based.



Programmed to receive



The reconfigurability of FPGAs provides an obvious way to prototype a chip before ordering out for actual silicon. And lots of chip designers do ad hoc prototyping with FPGAs. But there are a couple systems out there that are designed specifically to provide broad prototyping and accelerated verification capabilities across a wide range of designs. Neither of the ones making news recently is a new system, but each has its reasons for making some noise. [more]












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