FPGA Central

IC Journal Update




a techfocus media publication :: February 24, 2009 :: volume V, no. 08









FROM THE EDITOR



We’ve looked at some of the changes that have come to formal verification before, but it still seems like a big jump for some designers to go from no formal to the full package. This week we look at an effort OneSpin is making to make it easier for people to ease into the methodology, assuming that once you’ve gotten a bit of a taste, you’ll be hooked. In addition, we have an article from IDT sharing some of their experience dealing with design data management (DDM) systems that should be useful to those of you trying to put your design projects in order.

Thanks for reading! We love to get your feedback and suggestions; please send either or both to:
comments (AT) ICJournal (DOT) com. You can also make yourself heard publicly by going to our Journal Forums.

Bryon Moyer - Editor
IC Design and Verification Journal









EVENTS & ANNOUNCEMENTS











AMCC and DENX at EmbeddedWorld 2009, Nuremberg, Germany, March 3-5, 2009! Visit our co-exhibit in Hall 9, Booth 375 to learn how AMCC and DENX are driving new technologies and accelerating product development in the international embedded community.
See AMCC's New PowerPC 460EX Reference Design demo and the Arches Reference Design Dual PowerPC AMC Compliant demo




















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LATEST NEWS



February 24, 2009



MIPS Technologies Selects Berkeley Design Automation Analog FastSPICE™ Platform and AFS Nano™



Certess Announces the First C-Level Functional Qualification Tool



Synopsys, Powerchip and Nikon Collaborate on 42-nm Flash Memory Optimization



Teklatech’s FloorDirector™ Tool Compatible with Sigrity’s XcitePI Power Integrity Simulation Flow



Robotics Trends Announces RoboBusiness Conference & Exposition 2009 Academic Outreach Program



February 23, 2009



Lattice Accelerates Development Time With New Reference Designs Optimized For Popular MachXO PLD Family



Industry's First Low Power Verification Methodology Manual, Authored by ARM, Renesas Technology and Synopsys, is Now Available



Lattice Announces New Mixed-Signal Design Software Tool Suite



Lattice Announces ispLEVER 7.2 Service Pack 1 FPGA Design Tool Suite



Jasper Design Automation Introduces Design Activation Services To Promote IP and Design Reuse, Driving Higher Customer ROI



NXP Licenses ARM CortexTM-M0 Processor



February 19, 2009



EVE to Demonstrate ZeBu-Personal, zFAST at DVCon



Simulation Helps Keep One of World's Top Data Centers Cool



Agilent Technologies' SATA Compliance Test Software Provides Industry's First Automated 6-Gb/s Measurements



February 18, 2009



Mark Your Calendars: DVCon 2009 to Deliver Rich Technical Program



Imagination announces first member of new vector graphics IP core family
POWERVR™ VGX150 leads next wave of vector graphics processing











CURRENT FEATURE ARTICLES



Acquiring More Addicts
Easing into Formal Verification (Bryon Moyer)
Evaluating a Design Data Management System
by Scott Woods, Integrated Device Technology, Inc.
Standardising on Analogue
(Dick Selwood)
Maximizing Flash Lifetimes
A Look at Flash Management Strategies
(Bryon Moyer)
The Road Ahead
The ITRS Updates The Forecast (Bryon Moyer)
Open, Virtual and a Platform
(Dick Selwood)
Hijacking the Hijacker
Z-RAM Exploits Parasites (Bryon Moyer)




JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK Catapult C Synthesis Designing a JPEG Compression Engine. Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics).

CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)

CHALK TALK Creating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)



[click here for more webcasts]











Acquiring More Addicts
Easing into Formal Verification
(Bryon Moyer)

Last summer we took a look at the fact that formal verification is seeing something of a repositioning and resurgence. The holiest of holies is the ability to verify that all possible use cases of a piece of logic have been specified and that all possible outcomes of those use cases have been verified to operate as desired.

It can be viewed as a big jump from no formal verification to the complete set; it’s a change to the design flow, and we all know that the hardest thing to bring about is a methodology change. One of the players in this field, OneSpin Solutions, has brought some marketing magic to this problem in order to make formal more accessible to more designers. I’m sure they wouldn’t want to think of it this way, but they’ve realized that they need to apply a series of gateway drugs to get you hooked, rather than approaching you straight-off with a big-ol’ honkin’ scary-lookin’ needle. [more]







Evaluating a Design Data Management System
by Scott Woods, Integrated Device Technology, Inc.

Evaluating any EDA tool has several challenges. You have several tools and vendors to choose from. You have to get past the marketing hype to determine what is really important to you and whether the supported feature set meets your requirements. Finally, you have to make sure that the features you need perform as advertised. And, of course, you have to do this evaluation while juggling all your other tasks.

Evaluating a design data management (DDM) system is further complicated by the fact that it is groupware. To be effective, all the engineers on the project must adopt the system. [more]






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