FPGA Central

Hello

We are pleased to share with you the latest Verification
news and information and hope you enjoy this month's
issue.

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IN THIS ISSUE:

> News
> Technical Papers
> Technical Events

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> News

* Applied Micro Circuits Corporation (AMCC) Adopts 0-In
for Their Complex Clock Domain Crossing Verification

A recent high-performance network processor presented
a new challenge for the AMCC team. The processor
consisted of a PowerPC embedded processor core and a
multi-clock domain SoC that includes Ethernet and other
standard interfaces. Both parts required CDC
verification, but the SoC was more challenging because
of the complexity of its clock domains and the signals
that pass between them. It was clear that this design
required a more sophisticated and comprehensive CDC
verification solution than they had used before.

http://lyris.mentor-info.com/t/11063...74/12310/3496/

> Technical Papers

* The Value of Combining Processor-driven Testbenches
with Traditional HDL Testbenches
This article discusses three distinct methods of
developing and executing processor-driven tests, which
are test vectors driven into the design via the
processor bus. For designs that incorporate or
interface to an embedded CPU, processor-driven tests
can be a valuable addition to the functional
verification test suite, because they can detect design
errors that may be missed by more traditional HDL
testbenches.
http://lyris.mentor-info.com/t/11063...74/12311/3320/

* Harvesting Real Productivity from Simulation Farms
This paper examines a graph-based technique for
describing and spatially distributing a verification
task efficiently across multiple machines in a
simulation farm. Design examples are used to explore
typical applications of this technique.
http://lyris.mentor-info.com/t/11063...74/12312/3319/

> Technical Events

* Easily Inspect & Find Defects in Your Processor-Based
Design and Testbench Web Seminar
July 15

This seminar demonstrates how Codelink accelerates the
diagnostic phase of processor-based design using
processor-driven tests.

More information and registration
http://lyris.mentor-info.com/t/11063...74/12313/3497/

* "What is Intelligent Testbench Automation?"
Online Seminar

This archived event discusses the methods behind
Mentor's intelligent testbench automation tool,
inFact. It presents how to apply different verification
strategies without having to rewrite the entire
testbench and how intelligent testbench components fit
into an overall verification architecture.

View at your convenience
http://lyris.mentor-info.com/t/11063...74/12315/3498/

* DAC 2009
July 27-30 - San Francisco, CA

Come see us at DAC 2009 in Booth #3567.

Featured Verification sessions covering:


- Low Power SoC Verification with a UPF-Based Flow
- SystemVerilog Verification from Requirements to
Coverage Closure
- The OVM: The Methodology Platform

http://lyris.mentor-info.com/t/11063...74/12316/3499/

* Combining Formal Model Checking and Simulation for
Verification Closure Web Seminar
July 14

This web seminar discusses a methodology that
incorporates both property checking and simulation in a
integrated, synergistic fashion. By combining the
strength of each approach, this methodology finds more
bugs faster, helps designers reach coverage closure,
and as such enables designers to deliver higher quality
design with less overall effort.

More information and registration
http://lyris.mentor-info.com/t/11063...74/12317/3265/

Have a friend or colleague that would like this
newsletter?
Feel free to pass it on!

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Tom Fitzpatrick
Verification Technologist

Mentor Graphics Corporation
http://lyris.mentor-info.com/t/11063...74/12318/1762/

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