FPGA Central

FPGA Journal Update




a techfocus media publication :: June 30, 2009 :: volume XXIII, no. 13







FROM THE EDITOR 



This week, Altera changed the game in low-cost FPGAs with Cyclone III LS.  The new family boasts the largest density we've seen in a low-cost FPGA, very low static power, new security features, and a clever design partitioning capability.  Our latest feature has the details.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.

Kevin Morris – Editor in Chief
Techfocus Media, Inc.









EVENTS & ANNOUNCEMENTS











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LATEST NEWS

June 30, 2009

Broadcast Video Test Equipment Leader PHABRIX Selects National Semiconductor's 3-Gbps SDI Family

Curtiss-Wright Controls Announces Successful Environmental Testing of CHAMP-FX2 VPX and XMC-442 FPGA-based Application Accelerator Modules

eInfochips Announces VMM-Enabled MIPI® CSI-2, DSI & HSI and SDIO Verification IP for the Synopsys® DesignWare® Verification IP Alliance Program

46th DAC Announces Power-Scavenging Topic Wins First-Ever Community-Selected Panel Vote

June 29, 2009

Altera Announces New Cyclone III LS FPGAs

New Package Option For Lattice MachXO PLD Family Reduces Cost And Board Area

Mentor Graphics Extends Catapult C with Support for Control Logic to Enable Full-Chip High-Level Synthesis

SMSC Introduces Low-Cost, High Performance I/O Port Expander and DTCP Co-Processor for MOST® Networks

Aquantia deploys Synopsys IC Validator and IC Compiler for 40nm quad 10GBASE-T design

June 26, 2009

LinuxLink from Timesys Simplifies Development of Linux Products Using Xilinx Virtex-4 and Virtex-5 FPGAs

June 25, 2009

The Latest Report on the Opportunities for ARM in Embedded Processing is Available Today

Achilles Test Systems Founders Present at DAC Conference

Curtiss-Wright Controls Announces New Board Level Products Supporting Xilinx Virtex-6 FPGAs

Designers to Share Real-World Experiences at the 46th Design Automation Conference User Track

June 24, 2009

Xilinx Accelerates Development of Next-Generation Systems with Industry’s First Deployment of Targeted Design Platforms

Achronix selects Synopsys as its leading EDA partner

Mentor Graphics Announces Logic and Physical Synthesis Support for Xilinx Virtex-6 and Spartan-6 FPGAs

IAR Embedded Workbench drives up to 30% additional power savings for Atmel’s new picoPower AVR32 family

Verific Design Automation Tools Deliver Industry-Leading RTL Language Support for Xilinx ISE Design Suite








CURRENT FEATURE ARTICLES



Locking Down Power
Altera Rolls Out Cyclone III LS
(Kevin Morris)
Power Primer
Is That My FPGA Burning?
(Kevin Morris)
The Simulizater Is Not God
A Twist on Simulate Versus Synthesize
by Ben Jordan, Altium Ltd.
Climbing the Pyramid
Saving Engineering Education
(Kevin Morris)
Bounding Raptors
(Dick Selwood)



JOURNAL WEBCASTS



CHALK TALK Power Estimation in a High-Level DSP Design Flow . Want your DSP design to consume less power?  Join Amelia Dalton as she talks with Tim Vanevenhoven of Xilinx about new methods for estimating and reducing power consumption in FPGA-based DSP designs. (Xilinx)

Designing for Low Power with Actel Flash FPGAs. The webcast features: the benefits of flash versus SRAM technologies; an introduction to Actel’s low-power FPGA families; software tools for low-power design; low-power design tricks; hardware for evaluating low-power designs. (Actel)

CHALK TALK FPGA - PCB Co-Design Done The Right Way. Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs. (Cadence)

FPGAs Verifying FPGAs. Advanced FPGAs now require a more rigorous verification approach or designers risk spending months in the lab trying to debug their designs in-system. Learn how Device Native® verification integrates seamlessly with your existing FPGA design tools and delivers significant productivity improvements for verification and debug. (GateRocket)

CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)




[click here for more webcasts]












Locking Down Power
Altera Rolls Out Cyclone III LS
(Kevin Morris)

We've talked a lot in the past about the process node tango danced by the two largest FPGA companies.  With each step, one leads and the other follows - usually with a twist.  Unlike the traditional tango, however, we often have the lead changing with each subsequent move - a scheme certain to confuse most dance fans, but a situation that makes the FPGA market far more interesting.  Also, unlike in the traditional tango, both dancers are doing their dead-level best to knock the other one off their feet.  That makes things really exciting - from our perspective, at least.



Let's review the normal steps, then see how the dance is progressing.  



Cue music:  Let's go with Astor Piazzola's "Libertango"...



five... six... seven... eight...



1998 - Xilinx launches "Spartan" - the first low-cost FPGA family.  Altera hasn't heard the music start and is still in the dressing room adjusting wardrobe.



1999 - Xilinx takes the second step with widespread deployment of Spartan-II.



2002 - Altera hears the music, runs out onto the floor, and steps squarely on Xilinx's toe with the introduction of 130nm Cyclone.  Xilinx trips, falls down and twists an ankle.



2003 - Xilinx struggles back to its feet and takes a big gamble, launching the Spartan-3 90nm before their high-end Virtex-4 devices.  It was probably much easier to bring up the smaller, simpler, low-cost device than the big, complex, high-end family.  Plus, the smaller size of the die means more die per wafer and correspondingly higher yields.  The gambit works pretty well, and Spartan-3 starts recovering some market share in the low-cost FPGA space.



2003 - Altera spins around with a flare and executes a "Gancho" step, launching the 90nm Cyclone II.  Now we are once again at parity on process node, and Altera has had a chance to read Xilinx's data sheet before announcing their own.  Xilinx makes a substitution, sending the silicon design team to the trainer for a knee-wrap.  Xilinx marketing takes over and works to counter Altera's move. [more]










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