FPGA Journal Update
a techfocus media publication :: June 16, 2009 :: volume XXIII, no. 11
FROM THE EDITOR
"Students aren't studying engineering anymore." "All the good projects are being outsourced to emerging countries." "The best engineers are being laid off." "We're facing a huge engineering talent shortage." - Quotes like these bounce around the hallways and over the cubicle walls as if they were simple facts. Of course, they can't all be true, and in fact, most of them aren't. Engineering is a profession that constantly re-defines itself, and in doing so, re-shapes the demands on the educational system that produces new engineers. How does our system need to adapt, and what can we, as practicing engineers, do to help?
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Kevin Morris – Editor in Chief
Techfocus Media, Inc.
EVENTS & ANNOUNCEMENTS
Stratix IV GT FPGAs shipping now!
Altera’s Stratix IV GT FPGAs offer the only single-chipFPGA solution with integrated 11.3-Gbps transceivers—the industry’s highest density and highest system bandwidth for 10G/40G/100G applications.
Learn More!
FPGA Design Survey:
FPGA Designers, please take a few minutes to complete this short survey and tell us about your
FPGA development environment. Respondents who complete the survey and provide their contact information will be entered into a drawing to win one of fifty $25.00 gift certificates from Amazon.com
Click here to take the short survey
STAND OUT: MOVE TO ALTIUM'S NEXT GENERATION ELECTRONICS DESIGN SOLUTION. Altium Designer for US$195 per month with continuous updates.
FPGA implementation, schematic capture and PCB layout in a single application, out of the box!
Find out about other license options and download a 30-day trial here
Take our SUPER QUICK,
JUST A COUPLE OF QUESTIONS,
WON'T TAKE MUCH TIME AT ALL (WE PROMISE)
2009 Journal Reader Survey.
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LATEST NEWS
June 16, 2009
Altera Corporation Deploys Benergy® Platform to Streamline Benefits Management & Simplify Open Enrollment Process
Agilent Technologies’ Digital Measurement Forum Focuses on Trends Influencing Future of Industry
June 15, 2009
Lattice Announces Updates And Enhancements To Its FPGA Design Tool Suite
Synopsys continues Galaxy Custom Designer momentum with 2009.06 release
Arteris and Duolog Streamline SOC Integration Design Flow
SiliconBlue Launches “Turbo” Speed Version of Ultra-Low Power iCE65 mobileFPGA Family
Cypress Enters High-Performance Clock Generator Market With Industry’s Most Flexible Ultra-Low Phase Jitter Solution
BroadLogic Paves the Way to a New Era in Narrowcast and Unicast Cable Services with the Industry’s First Ultra-Dense QAM Modulator Chip
June 11, 2009
EDA Standards Organizations Accellera and The SPIRIT Consortium Announce Plans to Merge
June 10, 2009
Gennum's Snowbush IP Group Delivers the Industry's First PCI Expess 3.0 PHY IP on TSMC 40nm Process
ARM Utilizes eASIC Devices To Validate Cortex-A MPCore Multicore Processor-Based Devices
Operating Systems Used in Embedded Systems - Volume 6: End-User Data on Operating Systems and Multi-Core Components & Tools
CURRENT FEATURE ARTICLES
Climbing the Pyramid
Saving Engineering Education
(Kevin Morris)
Bounding Raptors
(Dick Selwood)
FPGA the Holistic Way
Flow Integration from Concept to PCB
by Ehab Mohsen, Mentor Graphics Corporation
Akya Reconfigurable Logic
Roll Your Own
FPGA - Sort of
(Kevin Morris)
Xilinx Strengthens Its Defenses
New
FPGA Families for Mil/Aero
(Kevin Morris)
Cadence Uses the F Word
FPGA PCB Co-design Debuts
(Kevin Morris)
JOURNAL WEBCASTS
NEW! Designing for Low Power with Actel Flash FPGAs. The webcast features: the benefits of flash versus SRAM technologies; an introduction to Actel’s low-power
FPGA families; software tools for low-power design; low-power design tricks; hardware for evaluating low-power designs. (Actel)
CHALK TALK
FPGA - PCB Co-Design Done The Right Way. Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs. (Cadence)
FPGAs Verifying FPGAs. Advanced FPGAs now require a more rigorous verification approach or designers risk spending months in the lab trying to debug their designs in-system. Learn how Device Native® verification integrates seamlessly with your existing
FPGA design tools and delivers significant productivity improvements for verification and debug. (GateRocket)
CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with
FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)
CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)
[click here for more webcasts]
Climbing the Pyramid
Saving Engineering Education
(Kevin Morris)
When most of us went to engineering school, we planned to immerse ourselves in the ocean of technology. Our education started with foundations of mathematics and science, and then, like some giant tech-history-TiVo, fast-forwarded us through centuries of experience and innovation to get us to a point somewhere near the state-of-the-art at the time of our graduation.
We soon learned that our engineering degree was simply a license to learn, however. In an environment of exponential change (as evidenced by Moore's Law), the actual technology we mastered in our educational process was probably obsolete before our first day of professional engineering work. It's not that our education wasn't valuable. It's just that the part we needed had nothing to do with the using the TEGAS simulator, throwing down transistors on a CALMA station, or our mad FORTRAN coding skills.
Technology is like a pyramid. Each generation of engineers must first understand the architecture, then carry their stones to the top of that structure, building on the foundation of their predecessors. As that pyramid grows, the climb gets more challenging for each subsequent stratum. Today's electrical engineering students start at the same level we all did - Kirchoff's laws, Karnaugh maps, and Calculus. However, they have to go zooming through countless layers of learning on top of those concepts - many of which didn't exist even the year before. Somehow, it all still has to fit in a four- - er, five- - uh, seven-year curriculum. Just as the surface of the pyramid expands exponentially as the structure grows, so does the number and specialization of engineers required to create and sustain each new level of technology. Even though most of us don't have to worry much about simulated annealing algorithms! for placement as we do our system-on-
FPGA design, somewhere there has to be an engineer who has dedicated a major chunk of his or her career to understanding, applying, and furthering that concept in order for us to be successful at our job.
At the same time, however, each layer of the pyramid brings us increased leverage and improved productivity. Today, with a comparatively small amount of education, I can buy a $99
FPGA development board, download some free tools and IP, and create an immensely capable electronic system that only a decade or two ago would have required dozens of engineers and millions in development costs. This hyper-productivity has given rise to a new breed of engineer - the solution surfer. The solution surfer doesn't understand or even care about the layers of technology underlying his or her project. The solution surfer simply rides the crest of the technology wave, picking and combining the tools and IP required to achieve a desired result. [
more]
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