FPGA Central

FPGA Journal Update




a techfocus media publication :: June 9, 2009 :: volume XXIII, no. 10











FROM THE EDITOR 





From offices just outside Paris and in Silicon Valley, a company aims to take on the existing FPGA vendors on their most treasured turf. Dick Selwood has been talking to Abound Logic about hierarchy and Raptors.

Also new this week, Ehab Mohsen of Mentor Graphics tells us how a holistic approach to FPGA design can help eliminate a lot of those messy recurring problems that always sneak into our design process.  Tools and processes that are integrated by design can save a lot of the headaches that come from an ad-hoc design methodology.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.

Kevin Morris – Editor in Chief
Techfocus Media, Inc.











EVENTS & ANNOUNCEMENTS











Low power, low cost, small form factor, and reprogrammability—now you can have it all. Targeting high-volume applications and the portable market, Actel IGLOO® nano and ProASIC®3 nano FPGAs enable you to take your design ideas to market profitability in nano time.

Read the white papers and watch the webcast.





















FPGA Design Survey: FPGA Designers, please take a few minutes to complete this short survey and tell us about your FPGA development environment. Respondents who complete the survey and provide their contact information will be entered into a drawing to win one of fifty $25.00 gift certificates from Amazon.com

Click here to take the short survey





















STAND OUT: MOVE TO ALTIUM'S NEXT GENERATION ELECTRONICS DESIGN SOLUTION. Altium Designer for US$195 per month with continuous updates. FPGA implementation, schematic capture and PCB layout in a single application, out of the box!

Find out about other license options and download a 30-day trial here





















Take our BRAND NEW
SUPER QUICK, JUST A COUPLE OF QUESTIONS,
WON'T TAKE MUCH TIME AT ALL (WE PROMISE)
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LATEST NEWS



June 9, 2009



TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow



"Innovative" products from Kane Computing Ltd



Algotronix provides AES encryption over USB with new reference designs



Sidense OTP Memory IP Enables SpectraLinear Non-Volatile Programmable PC Clock Family



Synfora Introduces PICO Extreme Power for Low Power Applications



EMA Integrates Newark’s Online Electronic Components Database with Cadence OrCAD Capture CIS



June 8, 2009



Lattice Announces New Automotive Qualified Chip Scale 132 BGA Packaging For The LatticeXP2 Family



Synopsys enables system design interoperability with System-Level Catalyst Program



Memory Applications, Packaging & Integration Trends 2009 Report: How 3-D Integration Will Challenge and Reshape the Memory Industry



June 4, 2009



Full-day X-fest technical seminars to be delivered in 36 cities worldwide



eInfochips Announces DDR2 SDRAM SystemVerilog Memory Model Generator Tool



SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development



June 3, 2009



Synopsys' Eclypse Low Power Solution Enables Fujitsu Microelectronics to Cut Design Cycle by 30 Percent



Altera Eases Development of 40-nm FPGAs with Stratix IV GX FPGA Development Kit



Synopsys Announces First DDR3 IP Verified in Silicon at 1600 Megabits per Second








CURRENT FEATURE ARTICLES 



Bounding Raptors
(Dick Selwood)
FPGA the Holistic Way
Flow Integration from Concept to PCB
by Ehab Mohsen, Mentor Graphics Corporation
Akya Reconfigurable Logic
Roll Your Own FPGA - Sort of  
(Kevin Morris)
Xilinx Strengthens Its Defenses
New FPGA Families for Mil/Aero
(Kevin Morris)
Cadence Uses the F Word
FPGA PCB Co-design Debuts
(Kevin Morris)
Fusion Finds its Groove
Actel Sees Applications for FPGA/Analog Hybrid
(Kevin Morris)

JOURNAL WEBCASTS 



CHALK TALK FPGA - PCB Co-Design Done The Right Way. Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs. (Cadence)

FPGAs Verifying FPGAs. Advanced FPGAs now require a more rigorous verification approach or designers risk spending months in the lab trying to debug their designs in-system. Learn how Device Native® verification integrates seamlessly with your existing FPGA design tools and delivers significant productivity improvements for verification and debug. (GateRocket)

CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)

CHALK TALK Simplified Verification of DSP Algorithms in Hardware. Moving algorithms from MATLAB to FPGAs? Join Amelia Dalton as she explores options for verifying DSP designs implemented in FPGAs with Tim Vanevenhoven from Xilinx. (Xilinx)



[click here for more webcasts]












Bounding Raptors
(Dick Selwood)

“With a bound he was free,” was always the way to get your hero out of a difficult position. You know the sort of thing – the hero is tied hand and foot in a cellar that floods on every tide. The tide is rising. The heroine is at the mercy of the evil villain who is twirling his mustachios in anticipation. “And, with a bound, the hero was free.” He shatters the cellar door with a karate kick, fells the villain with a straight right to the jaw, and sweeps the heroine into his arms and into the west, where they live happily ever after.

It would be surprising if that were the scenario that FPGA start-up M2000 had in mind when the company changed its name to Abound Logic in October 2008. (And of course the name wouldn’t have been chosen to get to the head of the alphabetical list of FPGA companies would it? No. Surely not?) But why start another FPGA company? Isn’t the market already fully served? The co-founders are certainly not novices – Frederic Reblewski and Olivier Lepape co-founded logic emulation company Meta Systems, which was acquired by Mentor Graphics and used field programmable fabric. Reblewski also founded Dune Technology, another logic emulation company, where Olivier developed the first proprietary FPGA architecture based on hierarchical switching networks as well as place & route algorithms. [more]






FPGA the Holistic Way
Flow Integration from Concept to PCB
by Ehab Mohsen, Mentor Graphics Corporation

In established FPGA development houses, managers look for predictability in product roll-out, from design creation to sign-off. This is no small feat. Development groups must deal not just with design complexity but also with project complexity.

Engineers with differing areas and levels expertise have to coordinate their own work, their tool flows, and a host of interdependencies. One might think the process would become smoother and more predictable from one project to the next, evolving toward a “standard methodology.” But no: history repeats itself and the same old problems never seem to go away—an update from one point tool breaks the flow with another, or switching to a different FPGA forces a rework of the entire process. The degree of integration across the flow varies, ranging from totally haphazard to completely methodical.  [more]










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